the serial digital interface during calibration or loaded

automatically from EEPROM at power-on. In this way

the device can be tested and configured during cali-

bration and test and the appropriate compensation val-

ues stored in internal EEPROM. The device will

auto-load the registers from EEPROM and be ready for

use without further configuration after each power-up.

The EEPROM is configured as an 8-bit wide array so

each of the 16-bit registers is stored as two 8-bit quan-

tities. The configuration register, FSOTCDAC and OTC-

Low-Cost Precision Sensor

Signal Conditioner

______________________________________________________________________________________

11

Table 1. EEPROM Memory Address Map

PAGE

LOW-BYTE

ADDRESS (hex)

HIGH-BYTE

ADDRESS (hex)

TEMP-INDEX[7:0]

(hex)

CONTENTS

000

001

00

0

03E

03F

1F

040

041

20

1

07E

07F

3F

080

081

40

2

0BE

0BF

5F

0C0

0C1

60

3

0FE

0FF

7F

100

101

80

4

13E

13F

9F

140

141

A0

15E

15F

AF to FF

ODAC

Lookup Table

160

161

Configuration

162

163

Reserved

164

165

OTCDAC

166

167

Reserved

168

169

FSOTCDAC

16A

16B

Control Location

16C

16D

5

17E

17F

180

181

19E

19F

52 General-Purpose

User Bytes

1A0

1A1

80

6

1BE

1BF

8F

1C0

1C1

90

7

1FE

1FF

AF to FF

200

201

00

8

23E

23F

1F

240

241

20

9

27E

27F

3F

280

281

40

A

2BE

2BF

5F

2C0

2C1

60

B

2FE

2FF

7F

FSODAC

Lookup Table