SPI/Microwire-Compatible

UART in QSOP-16

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7

The receiver section receives data in serial form. The

MAX3100 detects a start bit on a high-to-low RX transi-

tion (Figure 3). An internal clock samples data at 16

times the data rate. The start bit can occur as much as

one clock cycle before it is detected, as indicated by

the shaded portion. The state of the start bit is defined

as the majority of the 7th, 8th, and 9th sample of the

internal 16x baud clock. Subsequent bits are also

majority sampled. Receive data is stored in an 8-word

FIFO. The FIFO is cleared if it overflows.

The on-board oscillator can use a 1.8432MHz or

3.6864MHz crystal, or it can be driven at X1 with a 45%

to 55% duty-cycle square wave.

SPI Interface

The bit streams for DIN and DOUT consist of 16 bits,

with bits assigned as shown in the

MAX3100

Operations section. DOUT transitions on SCLK’s falling

edge, and DIN is latched on SCLK’s rising edge (Figure

4). Most operations, such as the clearing of internal

registers, are executed only on CS’s rising edge. The

DIN stream is monitored for its first two bits to tell the

UART the type of data transfer being executed (Write

Config, Read Config, Write Data, Read Data).

Only 16-bit words are expected. If CS goes high in the

middle of a transmission (any time before the 16th bit),

the sequence is aborted (i.e., data does not get written

to individual registers). Every time CS goes low, a new

16-bit stream is expected. An example of a write con-

figuration is shown in Figure 4.

1

RX

BAUD

BLOCK

2

3

4

5

6

7

8

9

ONE BAUD PERIOD

10

11

MAJORITY

CENTER

SAMPLER

12

13

14

15

16

A

Figure 3. Start-Bit Timing

1

CS

SCLK

DIN

DOUT

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DATA

UPDATED

1

1

FEN

SHDN

TM

RM

PM

RAM

IR

ST

PE

L

B3

B2

B1

B0

R

T

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Figure 4. SPI Interface (Write Configuration)