PUSB3TB6

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 1 — 19 August 2014

6 of 13

NXP Semiconductors

PUSB3TB6

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Fig 6.

Dynamic resistance with positive clamping;

typical values

Fig 7.

Dynamic resistance with negative clamping;

typical values

Fig 8.

Dynamic resistance with positive clamping;

typical values

Fig 9.

Dynamic resistance with negative clamping;

typical values

aaa-013508

06

4

2

2

1

3

4

I

(A)

0

aaa-013509

-6

0

-2

-4

-2

-3

-1

0

I

(A)

-4

012

8

4

aaa-013510

14

I

(A)

0

2

4

6

8

10

12

-12

0

-4

-8

aaa-013511

0

I

(A)

-14

-12

-10

-8

-6

-4

-2