Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

MIC706P Arkusz danych(PDF) 4 Page - Micrel Semiconductor

Numer części MIC706P
Szczegółowy opis  關P Supervisory Circuits
PDF  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  MICREL [Micrel Semiconductor]
Strona internetowa  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MIC706P Arkusz danych(HTML) 4 Page - Micrel Semiconductor

  MIC706P Datasheet HTML 1Page - Micrel Semiconductor MIC706P Datasheet HTML 2Page - Micrel Semiconductor MIC706P Datasheet HTML 3Page - Micrel Semiconductor MIC706P Datasheet HTML 4Page - Micrel Semiconductor MIC706P Datasheet HTML 5Page - Micrel Semiconductor MIC706P Datasheet HTML 6Page - Micrel Semiconductor MIC706P Datasheet HTML 7Page - Micrel Semiconductor MIC706P Datasheet HTML 8Page - Micrel Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 4 / 8 page
background image
4
Manual Reset Input forces reset outputs to assert when
pulled below 0.8V. An internal pull-up current of 250
µAon
this input forces it high when left floating. This input can
also be driven from TTL or CMOS logic.
Primary supply input, +5V.
IC ground pin, 0V reference.
Power fail input. Internally connected to the power fail
comparator which is referenced to 1.25V. The power fail
output (PFO) remains high if PFI is above 1.25V. PFI
should be connected to GND or VOUT if the power fail
comparator is not used.
Power fail output.
The power fail comparator is
independent of all other functions on this device.
Watchdog input. The WDI input monitors microprocessor
activity, an internal watchdog timer resets itself with each
transition on the watchdog input. If the WDI pin is held high
or low for longer than the watchdog timeout period, WDO is
forced to active low. The watchdog function cannot be
disabled.
No Connect
RESET is asserted if either VCC goes below the reset
threshold or by a low signal on the manual reset input (MR).
RESET remains asserted for one reset timeout period
(200ms) after VCC exceeds the reset threshold or after the
manual reset pin transitions from low to high. The
watchdog timer will not assert RESET unless WDO is
connected to MR.
Output for the watchdog timer. The watchdog timer resets
itself with each transition on the watchdog input. If the WDI
pin is held high or low for longer than the watchdog timeout
period, WDO is forced low. WDO will also be forced low if
VCC is below the reset threshold and will remain low until
VCC returns to a valid level.
RESET is the compliment of RESET and is asserted if
either VCC goes below the reset threshold or by a low
signal on the manual reset input (MR). RESET is suitable
for microprocessors systems that use an active high reset.
Pin No.
Pin Name
MIC706
MIC706P
MIC708
R/S/T
MR
11
1
VCC
22
2
GND
33
3
PFI
44
4
PFO
55
5
WDI
6
6
N/A
N/C
N/A
N/A
6
RESET
7
N/A
7
WDO
8
8
N/A
RESET
N/A
7
8
Pin Functions
MIC706P/R/S/T, MIC708R/S/T
µP Supervisory Circuits



Html Pages

1 2 3 4 5 6 7 8


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com