PIC16LC554 datasheet(40/96 Pages) MICROCHIP

40 / 96 page

PIC16C55X(A)

DS40143B-page 40

Preliminary

7.4

Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST)

7.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.6 V – 1.8 V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will eliminate

external RC components usually needed to create

Power-on Reset. A maximum rise time for VDD is

required. See Electrical Speciﬁcations for details.

The POR circuit does not produce internal reset when

VDD declines.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, etc.) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met.

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

7.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms (nominal)

time-out on power-up only, from POR. The Power-up

Timer operates on an internal RC oscillator. The chip is

kept in reset as long as PWRT is active. The PWRT

delay allows the VDD to rise to an acceptable level. A

conﬁguration bit, PWRTE can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-Up Time delay will vary from chip to chip and

due to VDD, temperature and process variation. See

DC parameters for details.

7.4.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on power-on reset or wake-up from

SLEEP.

7.4.4

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: First

PWRT time-out is invoked after POR has expired, then

OST is activated. The total time-out will vary based on

oscillator conﬁguration and PWRTE bit status. For

example, in RC mode with PWRTE bit erased (PWRT

disabled), there will be no time-out at all. Figure 7-8,

Figure 7-9 and Figure 7-10 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 7-9). This is useful for testing purposes or

to synchronize more than one PIC16C55X device oper-

ating in parallel.

Table 7-5 shows the reset conditions for some special

registers, while Table 7-6 shows the reset conditions for

all the registers.

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