ML2731

4

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

PIN DESCRIPTIONS

PIN CONFIGURATION

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

TOP VIEW

ML2731

16-Pin TSSOP (T16)

SINO

VCC

REGO

VBIAS

ICON

PAEN

NEGEN

CLKO

XOUT

XIN

PDN

VPA

C1

C2

VNEG

GND

1

SINO

O (ANLG)

Sine wave output. This pin is a low impedance output capable of

driving a 2k

W load. The signal is sourced with either a crystal

interfaced with on-chip components through XOIN (pin 15) and XOUT

(pin 16) or with a completely external oscillator through pin 15.

Taking PDN (pin 14) high switches off output

2

VCC

O (ANLG)

DC power supply

3

REGO

O (ANLG)

IC regulator output. This is the output from the on IC regulator. It is

disabled in the SLEEP mode of operation and enabled in all other

modes. The nominal output voltage is 2.9 V and it has a low

impedance output which can source up to 50mA

4

VBIAS

O (ANLG)

PA bias voltage output. This output has limited drive capability of 3mA

and is intended to drive the gate or bias of the PA

5

ICON

I (ANLG)

Reference current input. Used by the PA bias control loop to set the PA

current level. This input appears as a virtual ground

6

PAEN

I (CMOS)

PA Enable. Transitions from high to low on this pin activate the PA

current ramp up function, switch the PA voltage supply switch on and

enable the PA bias control loop. Transitions from low to high activate

the PA current ramp down function and switch the PA voltage supply

off

7

NEGEN

I (CMOS)

Negative Voltage Enable. In conjunction with PDN and PAEN, NEGEN

controls the operational mode of the IC and enables the negative

voltage generator circuits

8

CLKO

I (CMOS)

Clock output. The frequency is set with either a crystal interfaced with

on-chip components through XOIN (pin 15) and XOUT (pin 16) or with

a completely external oscillator through pin 15. CLKO switches off

when device goes into SLEEP mode when PDN is taken high

9

GND

GND

Ground

10

VNEG

O (ANLG)

Negative regulator output. This pin is one of the outputs of the negative

switching regulator. A capacitor connected serves as a current

reservoir. Typically a 100nF capacitor is connected between pin 10

and GND

11

C2

O (ANLG)

Noise Shunt. Negative voltage generator capacitor connection. This

output of the negative switching regulator shunts regulator noise to

ground using a 100nF bypass capacitor

Pin #

Signal Name

I/O

Description