ASM1834, ASM1834A, ASM1834D

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5

Detailed Description

Operation Power Monitor

The ASM1834 supervisors simultaneously detect

out−of−tolerance power supply conditions on both 3.3 V

outside the tolerance band, the reset for the falling supply

voltage becomes active. When the monitored supply returns

to an intolerance state, the reset remains active for

approximately 350 ms before returning to the inactive state.

On power−up, the reset signals are kept active for

approximately 350 ms after the power supply voltages have

reached the selected tolerance. This allows the power supply

and microprocessor to stabilize before the reset is removed.

All supply current for the ASM1834 devices is drawn

level. The outputs draw current from their input supplies

Figure 3. Timing Diagram: Power Up

(ASM1834D Only)

Figure 4. Timing Diagram: Power Down

(ASM1834D Only)

Reset Signal Polarity and Output Stage Structure

The ASM1834 and the ASM1834A supervisors have

active LOW reset signals. The ASM1834D reset outputs are

active HIGH.

The ASM1834 and the ASM1834D have CMOS

push−pull output stages. The ASM1834A has open drain

reset outputs.

Table 5.

Part #

RESET Polarity

Output Stage Configuration

ASM1834

LOW

Push−Pull

ASM1834U

LOW

Push−Pull

ASM1834S

LOW

Push−Pull

ASM1834A

LOW

Open Drain

ASM1834AU

LOW

Open Drain

ASM1834AS

LOW

Open Drain

ASM1834D

HIGH

Push−Pull

ASM1834DU

HIGH

Push−Pull

ASM1834DS

HIGH

Push−Pull

Manual Reset Operation

Push−button switch input, PBRST, allows the user to

override the internal trip point detection circuits and issue

reset signals. The pushbutton input is debounced and is

pulled HIGH through an internal 40 k

W resistor.

When at least one of the reset outputs is not asserted, a

push button initiated reset signal can be issued by holding

PBRST LOW for at least 2 ms. When PBRST is held LOW,

both resets become active and remain active for

approximately 350 ms after PBRST returns HIGH. (See

Figures 5 and 6.)