ACE9030MSLASHIWSLASHFP2N datasheet(19/39 Pages) MITEL

19 / 39 page

ACE9030

8·064 MHz Oscillator

Fig. 16 OSC8 Block Diagram

Table 2

Command

Crystal

PLL comp.

OSC8

Exact CLK8

Error

Data D2 D1 D0

frequency

divider

freq. (kHz)

divider

output (MHz)

(ppm)

1 0 0

12·8 MHz

÷100

128

÷63

8·064

0 1 1

14·85 MHz

÷825

÷448

8·064

1 0 1

14·85 MHz

÷337

44·065281

÷183

8·0639466

–7

1 1 0*

15·36 MHz

÷120

128

÷63

8·064

* Power up default

An 8·064 MHz oscillator OSC8 is provided to drive the

ACE9050 System Controller through pin CLK8. ACE9050

further drives the ACE9040 Audio Processor and the CL bus

clock via a

÷ 8 divider. OSC8 is locked to the crystal oscillator

by a phase locked loop with an external filter on pin C8B.

This loop can be programmed by a Set-up command to

give the correct output frequency with any of the normally used

crystals. Note that the same Set-up command uses DATA1 bit

5 for the lock logic and bits D7 and D6 for the Discriminator

programming:

DATA1

DATA2

DATA3

xxxxx D

2 D1 D0

10xxxxxx

xx1xxx00

where D

2 D1 D0 act as in table 2. At power-on reset the setting

is D

2 D1 D0 = 110, the values for a 15·36 MHz crystal, so that

the microcontroller is never clocked too fast with any of the

crystals and can then send the Set-up message to set D

2 D1

0 to the correct levels.

With a 14·85 MHz crystal it is not possible to both use a

high comparison frequency and get the exact 8·064 MHz

output, so two options are provided. The lower comparison

frequency will give the output exactly correct but will need

larger capacitors in the loop filter and the higher option allows

smaller capacitors and can improve close-in phase noise by

having a larger loop bandwidth, but gives a very small fre-

quency error - this error should have no effect in a practical

cellular terminal.

A Sleep command will not change the status of OSC8; if

enabled it will remain active when put into Sleep mode and

when returning to Normal mode. If the OSC8 oscillator is not

required it can be switched off by a Set-up command:

DATA1

DATA2

DATA3

xxxxxxxx

10xxxxx D

xxxxxx00

where DATA2 bit D0 at LOW gives OSC8 OFF or DATA2 bit

0 at HIGH gives OSC8 ON.

To allow for design and manufacturing tolerances the

VCO can be trimmed by two set-up commands, each of which

loads a 6 bit value in DATA1 into a control register. One sets

frequency “Range” (effectively the VCO gain but also with an

effect on the centre frequency):

DATA1

DATA2

DATA3

xx D

5 D4 D3 D2 D1 D0

10x1xxxx

xxxxxx00

The default values loaded by the power-on reset are

Offset = 0A

HEX and Range = 21HEX and were chosen to help

ensure that the output clock on CLK8 does not run faster than

8·064 MHz while better values are to be loaded. These default

values can usually be left unchanged for normal operation.

The output of the phase comparator charge pump is on

pin C8B so that an external loop filter can be connected. This

loop filter then drives the VCO control voltage, also through

DATA1

DATA2

DATA3

xx D

5 D4 D3 D2 D1 D0

10xx1xxx

xxxxxx00

The other sets frequency “Offset” (effectively the VCO

centre frequency but also with an effect on the gain):

RANGE &

OFFSET

FROM BUS

RATIO, FROM BUS

8.064 MHz OUTPUT FREQUENCY

PHASE

DETECTOR

C8B

RATIO, FROM BUS

: 63/183/448

EXTERNAL

LOOP

FILTER

CLK8

CHARGE

PUMPS

DOWN

µA

: 100/337/825

CRYSTAL

FREQUENCY

(XO)

VCO

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