MT8982AS datasheet(13/19 Pages) MITEL

13 / 19 page

ISO-CMOS

MT8982

2-43

† Timing is over recommended temperature & power supply voltages.

‡ Typical ﬁgures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

* High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

Figure 14a - TDM Bus Timing - F0o/Clock Timing

Figure 14b - ODE Timing

AC Electrical Characteristics† - TDM Bus (See Figures 13 and 14a, 14b). Voltages are with

respect to ground (VSS) unless otherwise stated.

Characteristics

Sym

Min

Typ‡

Max

Units

Test Conditions

Frame Pulse Input Setup Time

tfs

4 meg mode

Frame Pulse Input Hold Time

tfh

cycles

Serial Output Delay;

Active to Active

tsdaa

100

CL=50pF

Serial Output Delay;

Active to High Z

tsdaz

200

CL=50pF

RL=1kΩ*

Serial Output Delay;

High Z to Active

tsdza

150

CL=150pF

Serial Input Setup Time

tss

Serial Input Hold Time

tsh

Frame Pulse Output Delay

tfd

ODE Low to Serial Out High Z

tsaz

125

CL=50pF, RL=1kΩ*

ODE High to Serial Out Active

tsza

CL=50pF, RL=1kΩ

C4 Clock Pulse Width Low

tc4l

100

209

tc4 = 244 ns

C4 Clock Pulse Width High

tc4h

100

219

tc4 = 244 ns

C4 Clock Period

tc4

150

244

F0o (ST-BUS)

C4i

F0o (GCI)

tfd

tc4

tc4l

tc4h

tfd

ODE

STo0-1

tsaz

tsza

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