PDSP16256AC datasheet(16/28 Pages) MITEL

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PDSP16256

Using a Remote Master

When a remote master is used to load

coefficients, EPROM must be tied high and a

conventional peripheral interface is then provided. It

is not possible, however, to read coefficients already

stored. The master supplies an address and data

bus, and writes to the PDSP16256 occur under the

control of synchronous CS and WEN inputs. The

Coefficient Control Register pin (CCS) must be driven

by a master address line higher in significance than

A7:0. Both the WEN and CS signals must be low for

the load operation to occur. When loading the control

cycles, see Fig. 20. Since the internal write operation

is actually performed with the system clock, it is

necessary for the clock to be present during the

transfer.

The BYTE input defines whether coefficients are

loaded as a single 16 bit word or two 8-bit bytes. The

latter saves on connections to the remote master.

Address bits A7:0 are used in byte mode. 16-bit word

mode uses bits A6:0, A7 being redundant. When

writing in byte mode the least significant byte (A0 = 0)

must be written first followed by the most significant

byte (A0 = 1).

In byte mode the internal comparison between C15:12

and C11:8 is made, regardless of the state of EPROM .

For this reason pins C15:8 should all be tied low when

a remote master is used with byte transfers. This

ensures that the internal comparison gives equality

and allows the load operation to occur.

The address and coefficient buses plus

the WEN and CS signals must all meet the specified

set up and hold times with respect to the system

clock, see Fig 20 and Switching Characteristics.

This synchronous interface is optimum for the

majority of high end applications, when individual

coefficients must be updated at sample clock rates.

However, if the coefficients are to be loaded under

software control from a general purpose

microprocessor, the processor’s WRITE STROBE will

probably be asynchronous with the SCLK clock

used by the PDSP16256. In this case external

synchronising logic is needed, as shown in Fig.18.

Fig. 19 shows the recommended loading sequence

and filter operation initiation. The simplest technique

is to reset the device prior to loading a set of

coefficients. Coefficients may be loaded once BUSY

returns low or 22 cycles after RES is taken high.

When loading a device from a remote master the

control register must be loaded first followed by the

filter coefficients. Fig. 19 shows the required loading

sequence, two examples are given one for byte

mode the other for word mode. A gap of at least one

cycle must be left after loading the control register

before loading the first coefficient.

Filter operations are started by presenting the first

data word at the same time as raising signal FEN;

FRUN should always be low.

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