3

SP8714

OPERATING NOTES

The RF inputs are biased internally and are normally coupled to the signal source with suitable capaitors.

The output stage has a novel design and is intended to drive a CMOS synthesiser input. External pull-down resistors or

circuits are not required. The SP8714 is not suitable for driving TTL or similar devices.

The device will operate down to DC frequencies for non-sinusoidal signals provided that the input slew rate is better than

100V/

µs.

POWER DOWN (pin 7) is connected internally to a pull-up resistor. If the battery economy facility is not used, pin 7 should

Fig. 3 Typical input characteristics

Ratio

Modulus

Division

Select

Control

Ratio

(Pin 3)

(Pin 6)

LL

65

LH

64

HL

33

HH

32

TYPICAL

SENSITIVITY

TYPICAL

OVERLOAD

1000

800

600

400

200

0

500

1000

1500

2000

2500

3000

* Tested as specified in table of Electrical Characteristics

FREQUENCY (MHz)

GUARANTEED*

OPERATING WINDOW

Table 1 Truth table

Fig. 4 Modulus control timing diagram

RF INPUT

CLOCK

MODULUS

CONTROL

INPUTS

OUTPUT

t s

t h

32 (16)

32 (16) or 33 (17)

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