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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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Z86C21 Arkusz danych(PDF) 21 Page - Zilog, Inc. |
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Z86C21 Arkusz danych(HTML) 21 Page - Zilog, Inc. |
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21 / 35 page  21 Z86C21 MCU WITH 8K ROM AC CHARACTERISTICS External I/O or Memory Read or Write Timing Table T A = 0°C to +70°CTA = –40°C to +105°C 12 MHz 16 MHz 12 MHz 16 MHz No Symbol Parameter Min Max Min Max Min Max Min Max Units Notes 1 TdA(AS) Address Valid to /AS Rise Delay 35 25 35 25 ns [2,3] 2 TdAS(A) /AS Rise to Address Float Delay 45 35 45 35 ns [2,3] 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 250 180 250 180 ns [1,2,3] 4 TwAS /AS Low Width 55 40 55 40 ns [2,3] 5 TdAZ(DS) Address Float to /DS Fall 0000 ns 6 TwDSR /DS (Read) Low Width 185 135 185 135 ns [1,2,3] 7 TwDSW /DS (Write) Low Width 110 80 110 80 ns [1,2,3] 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 130 75 130 75 ns [1,2,3] 9 ThDR(DS) Read Data to /DS Rise Hold Time 0000 ns [2,3] 10 TdDS(A) /DS Rise to Address Active Delay 65 50 65 50 ns [2,3] 11 TdDS(AS) /DS Rise to /AS Fall Delay 45 35 45 35 ns [2,3] 12 TdR/W(AS) R//W Valid to /AS Rise Delay 30 20 33 25 ns [2,3] 13 TdDS(R/W) /DS Rise to R//W Not Valid 50 35 50 35 ns [2,3] 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 35 25 35 25 ns [2,3] 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 55 35 55 35 ns [2,3] 16 TdA(DR) Address Valid to Read Data Req’d Valid 310 230 310 230 ns [1,2,3] 17 TdAS(DS) /AS Rise to /DS Fall Delay 65 45 65 45 ns [2,3] 18 TdDM(AS) /DM Valid to /AS Rise Delay 50 30 50 30 ns [2,3] Clock Dependent Formulas Number Symbol Equation 1 TdA(AS) 0.40TpC + 0.32 2 TdAS(A) 0.59TpC – 3.25 3 TdAS(DR) 2.83TpC + 6.14 4 TwAS 0.66TpC – 1.65 6 TwDSR 2.33TpC – 10.56 7 TwDSW 1.27TpC + 1.67 8 TdDSR(DR) 1.97TpC – 42.5 10 TdDS(A) 0.8TpC 11 TdDS(AS) 0.59TpC – 3.14 12 TdR/W(AS) 0.4TpC 13 TdDS(R/W) 0.8TpC – 15 14 TdDW(DSW) 0.4TpC 15 TdDS(DW) 0.88TpC – 19 16 TdA(DR) 4TpC –20 17 TdAS(DS) 0.91TpC –10.7 18 TdDM(AS) 0.9TpC – 26.3 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0V for a logic 1 and 0.8V for a logic 0. |
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