ATmega16 datasheet(79/315 Pages) ATMEL

79 / 315 page

ATmega16(L)

2466E–AVR–10/02

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the

compare match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 74 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)

the compare match on the following timer clock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a compare match between TCNT0

and the OCR0 Register.

Table 41. Compare Output Mode, Phase Correct PWM Mode(1)

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on compare match when up-counting. Set OC0 on compare

match when downcounting.

Set OC0 on compare match when up-counting. Clear OC0 on compare

match when downcounting.

Table 42. Clock Select Bit Description

CS02

CS01

CS00

Description

No clock source (Timer/Counter stopped).

001

clkI/O/(No prescaling)

010

clk

I/O/8 (From prescaler)

011

clk

I/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clk

I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

Bit

765

432

TCNT0[7:0]

TCNT0

Read/Write

R/W

Initial Value

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