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AS3608 Arkusz danych(PDF) 51 Page - ams AG

Numer części AS3608
Szczegółowy opis  System PMU with HV Back Light Driver
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AMSCO [ams AG]
Strona internetowa  http://www.ams.com
Logo AMSCO - ams AG

AS3608 Arkusz danych(HTML) 51 Page - ams AG

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www.austriamicrosystems.com
Revision 1.03
50 - 67
AS3608 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
3:2
GPIO_DIMM_HBN_SEL
<1:0>
00
R/W
Selects input for external dimming or hibernation control
00: disable dimming or hibernation via GPIO
01: GPIO1
10: GPIO2
11: GPIO3
1:0
-
00
n/a
Table 40. BOOST_Cntr1 Register
Name
Base
Default
BOOST_Cntr1
2-wire serial
00h
Offset: 1Bh-1
DCDC step-up Control Register 1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
SU_ON
0
R/W
Enables the DCDC step-up regulator
0: SU switched off
1: SU switched on (will be reset if VFB exceeds the maximum and the
current drops to zero)
6-
0
n/a
5
SU_SLOWDIM
0
R/W
Selects the DCDC step-up regulator external dimming mode
0: for dimming frequencies <1kHz
1: for dimming frequencies >1kHz
4:3
SU_EXTDIM<1:0>
00
R/W
Selects the DCDC step-up external PWM dimming input
00: no ext. dimming
01: CURR1 controlled
10: CURR2 controlled
11: GPIO1/2/3 controlled (selected via GPIO_DIMM_HBN_SEL <1:0>)
2
SU_OVP_OFF
0
R/W
Disables the DCDC step-up over-voltage protection
0: SU OVP switched on
1: SU OVP switched off
1
SU_CURR_FB
0
R/W
Selects the DCDC step-up feedback mode
0: voltage FB via pin FBSU
1: current feedback via CURR1 or CURR2 (automatic select)
0
SU_FASTSKIP
0
R/W
Defines the DCDC step-up regulator output voltage at low loads, when pulse
skipping is active
0: Accurate output voltage, more ripple
1: Elevated output voltage, less ripple
Table 39. Clk_Cntr Register
Name
Base
Default
Clk_Cntr
2-wire serial
00h
Offset: 1Ah-2
Clock Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description



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