ADC14X250 datasheet(13/69 Pages) TI1

13 / 69 page

ADC14X250

www.ti.com

SLASE49 – DECEMBER 2015

Product Folder Links: ADC14X250

Submit Documentation Feedback

(1)

All timing specifications for the SPI given for VSPI = 1.8-V logic levels and a 5-pF capacitive load on the SDO output. Timing specification

may require larger margins for VSPI= 1.2 V.

(2)

This parameter is verified by design.

6.12 Timing Requirements

Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS. VSPI =

1.8 V

(1). Typical values are at T

A = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC SAMPLING INSTANT TIMING CHARACTERISTICS

Sampling Rate

Equal to FCLKIN / CLKDIV

250

MSPS

FCLKIN

Input Clock Frequency at CLKIN Inputs

MHz

CLKDIV = 1

250

CLKDIV = 2

100

500

CLKDIV = 4

200

1000

CLKDIV = 8

400

2000

Input clock (CLKIN) duty

cycle

CLKDIV = 1

CLKDIV = 2, 4, 8(2)

tLAT-ADC

ADC core latency

Delay from a reference sampling instant to the boundary of the

internal LMFC where the reference sample is the first sample of the

next transmitted multi-frame. In this device, the frame clock period is

equal to the sampling clock period.

8.5

Frame clock

cycles

Additive sampling aperture jitter

Depends on input CLKIN differential edge rate at the zero crossing,

dVSS/dt. Tested with 5 V/ns edge rate.

CLKDIV = 1

105

CLKDIV = 2, 4, 8

140

SYSREF TIMING CHARACTERISTICS

tPH-SYS

SYSREF assertion duration

Required duration of SYSREF assertion after rising edge event

Frame clock

cycles

tPL-SYS

SYSREF de-assertion duration

Required duration of SYSREF de-assertion after falling edge event

Frame clock

cycles

tS-SYS

SYSREF setup time

Relative to CLKIN rising edge

430

tH-SYS

SYSREF hold time

Relative to CLKIN rising edge

–100

JESD204B INTERFACE LINK TIMING CHARACTERISTICS

tD-LMFC

SYSREF to LMFC delay

Functional delay between SYSREF assertion latched and LMFC

frame boundary. Depends on CLKDIV setting. Multiply the delay value

by the CLKDIV factor to convert to units of CLKIN clock cycles.

Frame clock

cycles

CLKDIV = 1

3.5

CLKDIV = 2

CLKDIV = 4

3.75

CLKDIV = 8

3.625

tD-K28

LMFC to K28.5 delay

Functional delay between the start of the first K28.5 frame during

Code Group Synchronization at the serial output and the preceding

LMFC frame boundary.

7.4

Frame clock

cycles

tD-ILA

LMFC to ILA delay

Functional delay between the start of the first ILA frame during Initial

Lane Synchronization at the serial output and the preceding LMFC

frame boundary

7.4

tD-DATA

LMFC to valid data delay

Functional delay between the start of the first valid data frame at the

serial output and the preceding LMFC frame boundary.

7.4

ADC14X250 Arkusz danych(PDF) 13 Page - Texas Instruments

ADC14X250 Arkusz danych(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Arkusz danych Pobierz

Link URL