USB3300 datasheet(16/53 Pages) MICROCHIP

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USB3300

DS00001783B-page 16

 2014-2015 Microchip Technology Inc.

6.0

ARCHITECTURE OVERVIEW

The USB3300 architecture can be broken down into the following blocks shown in Figure 6-1, "Simplified USB3300

Architecture" below.

6.1

ULPI Digital

The USB3300 uses the industry standard ULPI digital interface to facilitate communication between the PHY and Link

(device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB

PHY to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI

interface requires only 12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification” document

(www.ulpi.org).

The following sections highlight the key operating modes of the USB3300 digital interface.

6.1.1

OVERVIEW

Figure 6-2 illustrates the block diagram of the ULPI digital functions. It should be noted that this PHY does not use a

“ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.

The advantage of a “wrapper less” architecture is that the PHY has a lower USB latency than a design which must first

wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification.

FIGURE 6-1:

SIMPLIFIED USB3300 ARCHITECTURE

ULPI Digital

OTG

Module

DATA[7:0]

Internal

Regulator &

POR

Bias

Gen.

CLKOUT

NXT

DIR

STP

VDD3.3

XTAL &

PLL

VBUS

VDD3.3

USB3300

RBIAS

HS XCVR

FS/LS

XCVR

Resistors

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