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LED2472G Arkusz danych(PDF) 15 Page - STMicroelectronics |
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LED2472G Arkusz danych(HTML) 15 Page - STMicroelectronics |
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15 / 39 page ![]() DocID024620 Rev 3 15/39 LED2472G Timing 6 Timing Figure 4. Timing for clock, serial-in, serial-out, latch enable and outputs Correct sampling of the data depends on the stability of the data at SDI on the rising edge of the clock signal and it is assured by a proper data setup and hold time (tSU(D) and th(D)), as shown in Figure 4. The same figure shows the propagation delay from CLK to SDO (tPLH/tPHL). Figure 4 describes also the minimum duration of CLK and LE pulses (tW(CLK) and tW(L), respectively) and the propagation delay from LE to OUTn (tPLH1/tPHL1 and tPLH2/tPHL2, respectively). Finally, Figure 5 also defines the turn-on and turn-off time (tof and tor) of the output voltage. Figure 5. OE and Outputs timing AM13690V1 |
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