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STAP16DPPS05XTTR Arkusz danych(PDF) 20 Page - STMicroelectronics |
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STAP16DPPS05XTTR Arkusz danych(HTML) 20 Page - STMicroelectronics |
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20 / 33 page ![]() Error detection mode functionality STAP16DPPS05 20/33 DocID024306 Rev 6 7 Error detection mode functionality 7.1 Phase one: entering error detection mode From the “normal mode” condition the device can switch to “error mode” by a logic sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and diagram: After these five CLK cycles, the device goes into the “error detection mode” and at the 6th rising edge of the CLK, the SDI data are ready for sampling. Table 13. Entering error detection mode - truth table CLK 1°2°3°4°5° OE/DM2 H L HHH LE/DM1 LLL H L Figure 18. Entering error detection mode - timing diagram CLK OE/DM2 LE/DM1 AM13668v1 |
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