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STAP16DPS05 Arkusz danych(PDF) 18 Page - STMicroelectronics |
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STAP16DPS05 Arkusz danych(HTML) 18 Page - STMicroelectronics |
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18 / 34 page ![]() Detection mode functionality STAP16DPS05 18/34 DocID024315 Rev 6 7 Detection mode functionality 7.1 Phase one: “entering in detection mode“ From the “normal mode” condition the device can switch to the “error mode” by a logic sequence on the OE/DM2 and LE/DM1 pins as shown in the following table and diagram: After these five CLK cycles the device goes into the “error detection mode” and at the 6th rising edge of CLK the SDI data are ready for sampling. Table 12. Entering in detection truth table CLK 1°2°3°4°5° OE/DM2 H L HHH LE/DM1 LLL H L Figure 14. Entering in detection timing diagram AM13677V1 |
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