RM46L430 datasheet(1/179 Pages) TI1

Numer części	RM46L430

Szczegółowy opis	16- and 32-Bit RISC Flash Microcontroller

PDF	179 Pages

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Producent	TI1 [Texas Instruments]

Strona internetowa	http://www.ti.com

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RM46L430, RM46L830

SPNS182C – SEPTEMBER 2012 – REVISED JUNE 2015

RM46Lx30 16- and 32-Bit RISC Flash Microcontroller

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Device Overview

1.1

Features

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• High-Performance Microcontroller for Safety-

• Enhanced Timing Peripherals for Motor Control

Critical Applications

– 7 Enhanced Pulse Width Modulator (ePWM)

– Dual CPUs Running in Lockstep

Modules

– ECC on Flash and RAM Interfaces

– 6 Enhanced Capture (eCAP) Modules

– Built-In Self-Test (BIST) for CPU and On-chip

– 2 Enhanced Quadrature Encoder Pulse (eQEP)

RAMs

Modules

– Error Signaling Module With Error Pin

• Two Next Generation High-End Timer (N2HET)

Modules

– Voltage and Clock Monitoring

– N2HET1: 32 Programmable Channels

• ARM® Cortex®-R4F 32-Bit RISC CPU

– N2HET2: 18 Programmable Channels

– 1.66 DMIPS/MHz With 8-Stage Pipeline

– 160-Word Instruction RAM Each With Parity

– FPU With Single- and Double-Precision

Protection

– 12-Region Memory Protection Unit (MPU)

– Each N2HET Includes Hardware Angle

– Open Architecture With Third-Party Support

Generator

• Operating Conditions

– Dedicated High-End Timer Transfer Unit (HTU)

– Up to 200-MHz System Clock

for Each N2HET

– Core Supply Voltage (VCC): 1.14 to 1.32 V

• Two 12-Bit Multibuffered Analog-to-Digital

– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

Converter (MibADC) Modules

• Integrated Memory

– ADC1: 24 Channels

– 1.25MB of Program Flash With ECC

– ADC2: 16 Channels Shared With ADC1

(RM46L830)

– 64 Result Buffers Each With Parity Protection

– 1MB of Program Flash With ECC (RM46L430)

• Multiple Communication Interfaces

– 192KB of RAM With ECC (RM46L830)

– USB

– 128KB of RAM With ECC (RM46L430)

•

2-Port USB Host Controller

– 64KB of Flash for Emulated EEPROM With

•

One Full-Speed USB Device Port

ECC

– Three CAN Controllers (DCANs)

• 16-Bit External Memory Interface (EMIF)

•

64 Mailboxes Each With Parity Protection

• Common Platform Architecture

•

Compliant to CAN Protocol Version 2.0A and

– Consistent Memory Map Across Family

2.0B

– Real-Time Interrupt (RTI) Timer (OS Timer)

– Inter-Integrated Circuit (I2C)

– 128-Channel Vectored Interrupt Module (VIM)

– Three Multibuffered Serial Peripheral Interface

– 2-Channel Cyclic Redundancy Checker (CRC)

(MibSPI) Modules

• Direct Memory Access (DMA) Controller

•

128 Words Each With Parity Protection

– 16 Channels and 32 Peripheral Requests

•

8 Transfer Groups

– Parity Protection for Control Packet RAM

– Up to Two Standard Serial Peripheral Interface

– DMA Accesses Protected by Dedicated MPU

(SPI) Modules

• Frequency-Modulated Phase-Locked Loop

– Two UART (SCI) Interfaces, One With Local

(FMPLL) With Built-In Slip Detector

Interconnect Network (LIN 2.1) Interface

• Separate Nonmodulating PLL

Support

• IEEE 1149.1 JTAG, Boundary Scan and ARM

• Packages

CoreSight™ Components

– 144-Pin Quad Flatpack (PGE) [Green]

• Advanced JTAG Security Module (AJSM)

– 337-Ball Grid Array (ZWT) [Green]

• Calibration Capabilities

– Parameter Overlay Module (POM)

• 16 General-Purpose Input/Output (GPIO) Pins

Capable of Generating Interrupts

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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