UT699 datasheet(29/41 Pages) AEROFLEX

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4.6 Timing Characteristics for PCI Interface

(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40

oC to 105oC)

Notes:

1. All outputs are measured using the load conditions shown in Figure 15.

2. High-Z defined as +/-300mV change from steady state.

3. Guaranteed by design.

Symbol

Description

Min

Max

Units

t171

PCI_CLK to output valid

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, PCI_DEVSEL, PCI_REQ, and

PCI_ARB_GNT[7:0])

213

t181,2

PCI_CLK to output valid from high-Z

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, and PCI_DEVSEL)

213

t191,2

PCI_CLK to output high-Z

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, and PCI_DEVSEL)

t20

Setup time to PCI_CLK

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, PCI_DEVSEL, PCI_IDSEL,

PCI_GNT, and PCI_ARB_REQ[7:0])

3--

t21

Hold time from PCI_CLK

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, PCI_DEVSEL, and

PCI_IDSEL)

1--

t223

PCI_CLKto RESET deassertion

PCI Clocks

t23a3

PCI_CLKto PCI_RST deassertion

PCI Clocks

t23b3

PCI_RST assertion to PCI_CLK idle

PCI Clocks

t243

PCI_RST assertion to output high-Z

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR,

PCI_FRAME, PCI_IRDY, PCI_TDRY,

PCI_STOP, and PCI_DEVSEL)

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