SP6137 datasheet(4/13 Pages) SIPEX

4 / 13 page

Date: 7/28/04

SP6137 Wide Input, 900KHz Synchronous PWM Controll

General Overview

The SP6137 is a fixed frequency, voltage mode,

synchronous PWM controller optimized for high

efficiency. The part has been designed to be

especially attractive for split plane applications

utilizing 5V to power the controller and 2.5V to

20V for step down conversion.

The heart of the SP6137 is a wide bandwidth

transconductance amplifier designed to accom-

modate Type II and Type III compensation

schemes. A precision 0.8V reference present on

the positive terminal of the error amplifier per-

mits the programming of the output voltage

down to 0.8V via the VFB pin. The output of the

error amplifier, COMP, compared to a 1.1V

peak-to-peak ramp is responsible for trailing

edge PWM control. This voltage ramp and PWM

control logic are governed by the internal oscil-

lator that accurately sets the PWM frequency to

900kHz.

FUNCTIONAL DIAGRAM

1.7 V

POWER OK ONCE LOGIC

COMPARATOR

ASYNC. STARTUP

0.4 V

THERMAL

FAULT

CLR

COUNT 20

CLOCK

PULSES

600 kHZ

CLK

CLOCK PULSE GENERATOR

GL HOLD OFF

SHUTDOWN

100% Protection Logic

RESET

DOMINANT

QPWM

CLK

SYNCHRONOUS

DRIVER

GND

2 GL

PWM LOOP

5 COMP

POS REF

FAULT

Logic

Delay

FAULT

UVIN

COUNTER

CLR

CC UVLO

VIN UVLO

REF OK

4.05 V OFF

4.25 V ON

2.50 V ON

2.20 V OFF

UVLO COMPARATORS

REF OK

0.25V

VPOS

VFBINT

PWRFLT

0.8V

CORE

REFERENCE

REF OK

THERMAL AND SHORT CIRCUIT PROTECTION

FAULT

145°C ON

REF OK

100ms Delay

CLK

MFLT

DOMINANT

SET

DOMINANT

SET

135°C OFF

DETECTION

SHORT CIRCUIT

SOFTSTART INPUT

RAMP = 1.1V

VFBINT

VPOS

Gm ERROR AMPLIFIER

9 GH

8 SWN

10 BST

VFB

10 µA

VCC

PWRFLT

MFLT

THEORY OF OPERATION

The SP6137 contains two unique control fea-

tures that are very powerful in distributed appli-

cations. First, asynchronous driver control is

enabled during start up to prohibit the low side

NFET from pulling down the output until the

high side NFET has attempted to turn on. Sec-

ond, a 100% duty cycle timeout ensures that the

low side NFET is periodically enhanced during

extended periods at 100% duty cycle. This guar-

antees the synchronized refreshing of the BST

capacitor during very large duty ratios.

The SP6137 also contains a number of valuable

protection features. A programmable input (VIN)

UVLO allows a user to set the exact value at

which the conversion voltage is at a safe point to

begin down conversion, and an internal VCC

UVLO ensures that the controller itself has

enough voltage to properly operate. Other pro-

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