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SP730 Arkusz danych(PDF) 3 Page - Sipex Corporation |
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SP730 Arkusz danych(HTML) 3 Page - Sipex Corporation |
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3 / 7 page ![]() 3 Date: 6/14/04 SP730 Microprocessor Supervisory Circuit © Copyright 2004 Sipex Corporation 5kΩ Internal pull up resistor Delay Circuit Output Driver Bandgap Reference VDD Comparator RESET FUNCTIONAL DIAGRAM TIMING DIAGRAM Figure 1: SP730 Timing Diagram RESET VDD tRPU VTRIP VOH VOH tRPD PIN NUMBER PIN NAME 3 PIN SOT-23 DESCRIPTION 1 RESET Active Low. This pin goes low whenever V DD falls below the reset threshold. 2V DD Supply input. 3 GND Ground. PIN DESCRIPTION |
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