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PI6C49016

Rev. B

06/25/13

PI6C49016

Low Power Networking Clock Generator

Pin List

Pin#

Pin Name

Pin Type

Pin Description

16

X1

XI

Crystal input. Connect to 25 MHz fundamental mode

crystal or clock

17

X2

XO

Crystal output. Connect to 25 MHz fundamental

mode crystal. Float for clock input

18

VDDX

Power

3.3V Supply Pin

19

VDDO

Power

125 MHz output supply voltage. Connect to +2.5 V.

20

125M

Output

125 MHz, +2.5 V LVCMOS output. Tri-stated with a

weak pull-down when disabled.

21

GND

Power

Ground

22

VDD

Power

3.3V Supply Pin

23

66.66M

Output

66.66 MHz LVCMOS output. Tri-stated with a weak

pull-down when disabled

24

GND

Power

Ground

25

VDD

Power

3.3V Supply Pin

26

GND

Power

Ground

27

NC

-

-

28

VDD

Power

3.3V Supply Pin

29

GND

Power

Ground

30

VDD

Power

3.3V Supply Pin

31

PCIE0N

Output

Differential 100 MHz PCI Express Clock output

32

PCIE0

Output

Differential 100 MHz PCI Express Clock output

33

PCIE1

Output

Differential 100 MHz PCI Express Clock output

34

PCIE1N

Output

Differential 100 MHz PCI Express Clock output

35

VDD

Power

3.3V Supply Pin

36

GND

Power

Ground

37

VDD

Power

3.3V Supply Pin

38

Cdd

Input

Input pin for off chip bypass capacitor. Connect to 0.01

μF capacitor

39

PCIE2N

Output

Differential 100 MHz PCI Express Clock output

40

PCIE2

Output

Differential 100 MHz PCI Express Clock output

Notes: VDD and GND Pins Layout Guide

1. Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close each VDD pin or its via

2. Connect all GND pins to package thermal pad which must be connected to the GND plane for better thermal distribution and signal conducting with reasonable

via count (>8)

13-0102