PI6C49019 datasheet(3/16 Pages) PERICOM

3 / 16 page

www.pericom.com

PI6C49019

Rev. B

06/25/13

PI6C49019

Low Power Networking Clock Generator

Pin List

Pin#

Pin Name

Pin Type

Pin Description

VDD

Power

3.3V Supply Pin

VDD

Power

3.3V Supply Pin

GND

Power

Ground

19M

Output

19.2 MHz LVCMOS output. Tri-state with weak pull-

down when disabled

VDD

Power

3.3V Supply Pin

GND

Power

Ground

PD_RESET

Input

Global reset input powers down PLLs plus tri-states

outputs and sets the I2C tables to their default state

when pulled low. Controlled by external POR.

Crystal input. Connect to 25 MHz fundamental mode

crystal or clock

Crystal output. Connect to 25 MHz fundamental

mode crystal. Float for clock input

VDD

Power

3.3V Supply Pin

VDDO2

Power

125 MHz output supply voltage. Connect to +2.5 V

125M/REF

Output

125 MHz or 25 MHz reference +2.5 V LVCMOS out-

put. Tri-stated with a weak pull-down when disabled

25M

Output

25 MHz +2.5 LVCMOS output. Tri-stated with a weak

pull-down when disabled

GND

Power

Ground

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

GND

Power

Ground

48M

Output

48 MHz LVCMOS output. Tri-state with weak pull-

down when disabled

VDD

Power

3.3V Supply Pin

GND

Power

Ground

VDD

Power

3.3V Supply Pin

PCIE0N

Output

Differential 100 MHz HCSL PCI Express Clock output

PCIE0

Output

Differential 100 MHz HCSL PCI Express Clock output

PCIE1

Output

Differential 100 MHz HCSL PCI Express Clock output

PCIE1N

Output

Differential 100 MHz HCSL PCI Express Clock output

VDD

Power

3.3V Supply Pin

GND

Power

Ground

13-0103

PI6C49019 Arkusz danych(PDF) 3 Page - Pericom Semiconductor Corporation

PI6C49019 Arkusz danych(HTML) 3 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Arkusz danych Pobierz

Link URL