LP3943

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SNVS256C – NOVMEBER 2003 – REVISED OCTOBER 2015

7.5 Programming

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

conditions are equivalent, function-wise.

7.5.3 Transferring Data

Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first.

The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by

an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the

9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an

acknowledge after each byte has been received.

an eighth bit which is a data direction bit (R/W). The LP3943 hardwires bits 7 to 4 and leaves bits 3 to 1

selectable, as shown in Figure 4. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The

LP3943 supports only a WRITE during chip addressing. The second byte selects the register to which the data is

written. The third byte contains data to write to the selected register.

Figure 4. Chip Address Byte

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