ADAV4601 datasheet(25/60 Pages) AD

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ADAV4601

Rev. B | Page 25 of 60

Examples

1000 0000 0000 0000 0000 0000 0000 = −16.0

1110 0000 0000 0000 0000 0000 0000 = −4.0

1111 1000 0000 0000 0000 0000 0000 = −1.0

1111 1110 0000 0000 0000 0000 0000 = −0.25

1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)

0000 0000 0000 0000 0000 0000 0000 = 0.0

0000 0010 0000 0000 0000 0000 0000 = +0.25

0000 1000 0000 0000 0000 0000 0000 = +1.0

0010 0000 0000 0000 0000 0000 0000 = +4.0

0111 1111 1111 1111 1111 1111 1111 = (+16.0 − 1 LSB)

The serial port accepts up to 24 bits on the input and is sign-

extended to the full 28 bits of the DSP core. This allows internal

gains of up to 24 dB without internal clipping.

A digital clipper circuit is used between the output of the DSP

core and the DACs or serial port outputs (see Figure 38). This

clips the top four bits of the signal to produce a 24-bit output

with a range of +1.0 (minus 1 LSB) to −1.0. Figure 38 shows

the maximum signal levels at each point in the data flow in

both binary and decibel levels.

4-BIT SIGN EXTENSION

DATA IN

1.23

(0dB)

1.23

(0dB)

1.23

(0dB)

5.23

(24dB)

5.23

(24dB)

SERIAL

PORT

SIGNAL

PROCESSING

(5.23 FORMAT)

DIGITAL

CLIPPER

Figure 38. Numeric Precision and Clipping Structure

ROMS AND REGISTERS

The ADAV4601 contains four ROMS: program, instruction,

parameter, and LUT. A default set of ROMs is stored on chip

and is loaded on power-up. A set of ROMs defining a custom

flow can be stored externally on an EEPROM and can be loaded

after power-up.

Program ROM

Program ROM is 42-bits wide and occupies Address 0x1400 to

Address 0x1FFF. This is where the audio flow generated in

SigmaStudio is stored.

Instruction ROM

Instruction ROM is 33-bits wide and occupies Address 0x3000

to Address 0x327F. This is where the application layer register

map is stored.

Parameter ROM

Parameter ROM is 28-bits wide and occupies Address 0x1000 to

Address 0x13FF. Default parameters for default flow and custom

flow are stored here.

LUT ROM

LUT ROM is 28-bits wide and occupies Address 0x4000 to

Address 0x57FF. This contains the parameters for both flows

combined.

SAFE LOADING TO PARAMETER RAM AND

TARGET/SLEW RAM

Up to five safe load registers can be loaded with parameter

RAM address data. The data is transferred to the requested

address when the RAM is idle. It is recommended to use this

method for dynamic updates during run time. For example, a

complete update of one biquad section can occur in one audio

frame. This method is not available for writing to the program

RAM or control registers.

There are ten safe load registers operating in pairs of five, where

five of them store addresses and five of them store data. To safe

load a register, move its address into a safe load address register

and move its data into the corresponding safe load data register. If it

is a parameter RAM, set Bit 4 in Register 0x0200 to 1 to initiate the

safe load. If it is a target/slew RAM, set Bit 5 in Register 0x0200

to 1 to initiate the safe load.

The safe load data registers are located from Address 0x2040 to

Address 0x2044 and are five-bytes wide.

The safe load address registers are located from Address 0x2045 to

Address 0x2049 and are two-bytes wide.

The last five instructions of the program RAM are used for the safe

load process; therefore, the program length should be limited to

2555 cycles (2560 − 5). It is guaranteed that the safe load occurs

within one LRCLK period (21 μs at fS = 48 kHz) of the initiate

safe transfer bit being set. Safe load only updates those safe load

registers that have been loaded with new data since the last safe

load operation. For example, if only two parameters or target

RAM locations are updated, it is only necessary to load two of

the safe load registers; the other safe load registers are ignored

because they contain old data.

READ/WRITE DATA FORMATS

The read/write formats of the control port are designed to be

byte oriented. This allows easy programming of common micro-

controller chips. To fit into a byte-oriented format, 0s are appended

to the data fields before the MSB to extend the data-word to

eight bits. For example, 28-bit words written to the parameter

RAM are appended with four leading 0s to equal 32 bits (4 bytes);

40-bit words written to the program RAM are not appended

with 0s because they are already a full five bytes. These zero-

padded data fields are appended to a 3-byte field consisting of a

7-bit chip address, a read/write bit, and a 16-bit RAM/register

address. The control port knows how many data bytes to expect

based on the address given in the first three bytes.

The total number of bytes for a single location write command

can vary from five bytes (for a control register write) to eight bytes

(for a program RAM write). Burst mode can be used to fill

contiguous register or RAM locations. A burst mode write begins

by writing the address and data of the first RAM or register

location to be written to. Rather than ending the control port

transaction (by issuing a stop command in I2C mode), as would

be done in a single-address write, the next data-word can be

written immediately without specifying its address.

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