CLC5523 datasheet(8/12 Pages) NSC

8 / 12 page

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Evaluation Boards

Evaluation boards are available for both the 8-pin DIP

and small outline package types.

Evaluation kits that

contain an evaluation board and CLC5523 samples can

be obtained by calling National Semiconductor’s

Customer Service Center at 1-800-272-9959. The 8-pin

DIP evaluation kit part number is CLC730065. The 8-pin

small outline evaluation kit part number is CLC730066.

The DIP evaluation kit has been designed to utilize axial

lead components. The small outline evaluation kit has

been designed to utilize surface mount components.

The circuit diagram shown in Figure 5, applies to both the

DIP and the small outline evaluation boards.

Gain

Control

Vin

GND

I-

-VCC

+VCC

Rin

Input

Signal

100

0.1

6.8

Wž

0.1

6.8

-5V

Output

* 25

W series resistor is not required on the

small outline device and does not appear on

the small outline board

Figure 5: Evaluation Board Schematic

Printed Circuit Board Layout

High frequency op amp performance is strongly

dependent on proper layout, proper resistive termination

and adequate power supply decoupling. The most impor-

tant layout points to follow are:

Use a ground plane

Bypass each power supply pin with these capacitors:

a high-quality 0.1

mF ceramic capacitor placed

less than 0.2” (5mm) from the pin

a 6.8

mF tantalum capacitor less than 2” (50mm)

from the pin

for the plastic DIP package, a high-quality

1000pF ceramic capacitor placed less than 0.1”

(3mm) from the pin

Capacitively bypassing power pins to a good ground plane

with a minimum of trace length (inductance) is necessary

for any high speed device, but it is particularly important for

the CLC5523.

Establish wide, low impedance, power supply traces

For the plastic DIP package, a 25

W resistor should

be connected from pin 4 to ground with a minimum

length trace

Minimize or eliminate sources of capacitance

between the Rf pin and the output pin. Avoid

adjacent feedthrough vias between the Rf and

output leads since such a geometry may give rise

to a significant source of capacitance.

Minimize trace and lead lengths for components

between the inverting and output pins

Remove ground plane 0.1” (3mm) from all

input/output pads

For prototyping, use flush-mount printed circuit

board pins;

never use high profile DIP sockets

To minimize high frequency distortion, other layout issues

need be addressed:

Short, equal length, low impedance power supply

return paths from the load to the supplies

avoid returning output ground currents near the

input stage.

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