CLC5632IM datasheet(13/19 Pages) NSC

13 / 19 page

Application Division (Continued)

AC Coupled Single Supply Operation

Figure 4, Figure 5, and Figure 6 show possible non-inverting

and inverting configurations for input signals that go below

0.8V DC.

The input is AC coupled to prevent the need for level shifting

the input signal at the source. The resistive voltage divider

biases the non-inverting input to V

CC ÷ 2 = 2.5V (For VCC =

+5V)

Dual Supply Operation

The CLC5632 operates on dual supplies as well as single

supplies. The non-inverting and inverting configurations are

shown in

Figure 7, , and .

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

2.5

Low frequency cutoff

2R C

g C

=−

where Rg = 1kΩ.

Note: Channel 2 not shown.

DS015003-42

FIGURE 4. AC Coupled, A

V = −1V/V Configuration

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

Note: Channel 2 not shown.

2.5

Low frequency cutoff

2R C

where R

in C

source

=>>

DS015003-43

FIGURE 5. AC Coupled, A

V = +1V/V Configuration

2.5

Low frequency cutoff

2R C

where R

in C

source

=>>

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

Note: Channel 2 not shown.

DS015003-44

FIGURE 6. AC Coupled, A

V = +2V/V Configuration

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

Note: Rb provides DC bias for the

non-inverting input. Select Rt to

yield desired Rin = Rt||1kΩ.

Channel 2 not shown.

6.8

µF

0.1

µF

VEE

DS015003-45

FIGURE 7. Dual Supply, A

V = −1V/V Configuration

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

Note: Channel 2 not shown.

6.8

µF

0.1

µF

VEE

DS015003-46

FIGURE 8. Dual Supply, A

V = +1V/V Configuration

Ω

CLC5632

0.1

µF

6.8

µF

Vin

VCC

Note: Channel 2 not shown.

6.8

µF

0.1

µF

VEE

DS015003-47

FIGURE 9. Dual Supply, A

V = +2V/V Configuration

CLC5632IM Arkusz danych(PDF) 13 Page - National Semiconductor (TI)

CLC5632IM Arkusz danych(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Arkusz danych Pobierz

Link URL