CLC5957PCASM datasheet(8/12 Pages) NSC

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Figures 5 and 6 show the clock interface schemes to

several other types of clock sources.

Figure 5: 5V CMOS Level Clock Scheme

Figure 6: TTL or 3V CMOS Level Clock Scheme

Digital Outputs and Level Select

Figure 7 depicts the digital output buffer and bias used in

the CLC5957. Although each of the twelve output bits

uses a controlled current buffer to limit supply transients,

it is recommended that parasitic loading of the outputs is

minimized. Because these output transients are harmoni-

cally related to the analog input signal, excessive loading

will degrade ADC performance at some frequencies.

Figure 7: CLC5957 Digital Outputs

The logic high level is slaved to the internal 2.4 voltage

reference. The OUTLEV control pin selects either a 3.3V

or 2.5V logic high level. An internal pullup resistor selects

the 3.3 volt level as the default when the OUTLEV pin is

left open. Grounding the OUTLEV pin selects the 2.5V

logic high level.

To ease user interface to subsequent digital circuitry, the

CLC5957 has a data valid clock output (DAV). In order to

match delays over IC processing variables, this digital

output also uses the same output buffer as the data bits.

The DAV clock output is simply a delayed version of the

ENCODE input clock. Since the ADC output data change

is slaved to the falling edge of the ENCODE clock, the

rising DAV clock edge occurs near the center of the data

valid window (or eye) regardless of the sampling frequency.

ENC

CLC5957

0.01

µF

ENC

CLC5957

0.01

µF

ENC

2.4Vref

GNDD

Digital

Signal

VCCD

Controlled Current

Output Buffer

Digital

Output

Level

Open = 3.3Vhi

GND = 2.5Vhi

CML to

CMOS

10k

Ω

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