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MPC875 Arkusz danych(PDF) 35 Page - Freescale Semiconductor, Inc |
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MPC875 Arkusz danych(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 84 page ![]() MPC875/MPC870 Hardware Specifications, Rev. 3.0 35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 21 provides the timing for the synchronous external master access controlled by the GPCM. Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM. Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 23 provides the timing for the asynchronous external master control signals negation. Figure 23. Asynchronous External Master—Control Signals Negation Timing CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx B41 B42 B40 B22 CLKOUT AS A[0:31], TSIZ[0:1], R/W CSx B39 B40 B22 AS CSx, WE[0:3], OE, GPLx, BS[0:3] B43 |
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