DP8224 datasheet(5/8 Pages) NSC

5 / 8 page

Functional Pin Definitions

The following describes the function of all of the DP8224

inputoutput pins Some of these descriptions reference in-

ternal circuits

INPUT SIGNALS

Crystal Connections (XTAL 1 and XTAL 2)

Two inputs

that connect an external crystal to the oscillator circuit of

the DP8224 Normally a fundamental mode crystal is used

to determine the basic operating frequency of the oscillator

However overtone mode crystals may also be used The

crystal frequency is 9 times the desired microprocessor

speed (that is crystal frequency equals 1tCY c 9) When

the crystal frequency is above 10 MHz a selected capacitor

(3 to 10 pF) may have to be connected in series with the

crystal to produce the exact desired frequency

Figure A

Tank

Allows the use of overtone mode crystals with the

oscillator circuit When an overtone mode crystal is used

the tank input connects to a parallel LC network that is ac

coupled to ground The formula for determining the reso-

nant frequency of this LC network is as follows

F e

0LC

Synchronizing (SYNC) Signal

When high indicates the

beginning of a new machine cycle The 8080A microproces-

sor outputs a status word (which describes the current ma-

chine cycle) onto its data bus during the first state (SYNC

interval) of each machine cycle

Reset In (RESIN)

Provides an automatic system reset and

start-up upon application of power as follows The RESIN

input which is obtained from the junction of an external RC

network that is connected between VCC and ground is rout-

ed to an internal Schmitt Trigger circuit This circuit converts

the slow transition of the power supply rise into a sharp

clean edge when its input reaches a predetermined value

When this occurs an internal D-type flip-flop is synchro-

nously reset thereby providing the RESET output signal dis-

cussed below

For manual system reset a momentary contact switch that

provides a low (ground) when closed is also connected to

the RESIN input

Ready In (RDYIN)

An asynchronous READY signal that is

re-clocked by a D-type flip-flop of the DP8224 to provide the

synchronous READY output discussed below

5 Volts

VCC supply

12 Volts

VDD supply

Ground

0 volt reference

OUTPUT SIGNALS

Oscillator (OSC)

A buffered oscillator signal that can be

used for external timing purposes

w1 and w2 Clocks Two non-TTL compatible clock phases

that provide nonoverlapping timing references for internal

storage elements and logic circuits of the 8080A microproc-

essor The two clock phases are produced by an internal

clock generator that consists of a divide-by-nine counter

and the associated decode gating logic

Figure B

w2 (TTL) Clock A TTL w2 clock phase that can be used for

external timing purposes

Status Strobe (STSTB)

Activated (low) at the start of each

new machine cycle The STSTB signal is generated by gat-

ing a high-level SYNC input with the w1A timing signal from

the internal clock generator of the DP8224 The STSTB sig-

nal is used to clock status information into the status latch

of the DP8228 system controller and bus driver

Reset

When the RESET signal is activated the content of

the program counter of the 8080A is cleared

After

RESET the program will start at location 0 in memory

Ready

The READY signal indicates to the 8080A that valid

memory or input data is available This signal is used to

synchronize the 8080A with slower memory or inputoutput

devices

Logic and Connection Diagrams

TLF8752 – 4

Dual-In-Line Package

TLF8752 – 5

Top View

Order Number DP8224J or DP8224N

See NS Package Number

J16A or N16A

DP8224 Arkusz danych(PDF) 5 Page - National Semiconductor (TI)

DP8224 Arkusz danych(HTML) 5 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8

Arkusz danych Pobierz

Link URL