BQ28550-R1 datasheet(18/42 Pages) TI1

18 / 42 page

Not Recommended for New Designs

bq28550-R1

SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014

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Feature Description (continued)

Acknowledge Bits: An Acknowledge bit (A) is required after each data transfer byte to ensure correct

communications. This occurs when the receiving device pulls the SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse), and keeps it low until the SCL returns low. There is also a No-

Acknowledge bit (N), which occurs when the receiver releases the SDA line (high) before the rising edge of

acknowledge-related clock pulse, and maintains the SDA line high until SCL returns low. The Acknowledge bit

indicates if a successful data transfer has occurred between the master and slave device. Monitoring this bit also

indicates an unsuccessful data transfer due to the receiving device being busy or as system fault occurrence.

Communication Format

A START command immediately followed by a STOP command is an illegal format.

MSB

Slave Address

R/W

Data

S = START Command

R/W = Read from slave device ("1") or Write to slave device ("0")

A = Acknowledge bit

P = STOP Command

Slave Address = 7-bit address field for register address

DATA = 8-bit data field

PEC = Packet Error Checking

Slave to Master

Master to Slave

Communication Format for Multi-Word with Packet Error Checking (PEC)

Table 2. Write Byte with PEC

Slave Address

Command

Data Byte

PEC

Code

Table 3. Write Word with PEC

Slave

Command

Data Byte

PEC

Address

Code

Low

High

Table 4. Read Byte with PEC

Slave

Command

Slave

Data Byte

PEC

Address

Code

Address

Table 5. Read Word with PEC

Slave Address

Command

Slave

Data

PEC

Code

Address

Byte

Low

High

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