| Zakładka z wyszukiwarką danych komponentów |
|
BQ78350DBT-R1 Arkusz danych(PDF) 4 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
BQ78350DBT-R1 Arkusz danych(HTML) 4 Page - Texas Instruments |
|
4 / 32 page ![]() bq78350-R1 SLUSCD0 – AUGUST 2015 www.ti.com Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME 10 SAFE O Active high output to enforce an additional level of safety protection (for example, fuse blow) SMBus data open-drain bidirectional pin used to transfer an address and data to and from the 11 SMBD I/OD bq78350-R1 Active high voltage translation enable. This open drain signal is used to switch the input voltage 12 VEN O divider on/off to reduce the power consumption of the BAT translation divider network. SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq78350- 13 SMBC I/OD R1 Display control for the LEDs. This pin is typically connected to bq78350-R1 REGOUT via a 100- 14 DISP I K Ω resistor and a push-button switch connect to VSS. Not used with LCD display enabled and can be tied to VSS. 15 PWRM O Power mode state indicator open drain output LED1/LCD1 display segment that drives an external LED/LCD, depending on the firmware 16 LED1 O configuration LED2/LCD2 display segment that drives an external LED/LCD, depending on the firmware 17 LED2 O configuration LED3/LCD3 display segment that drives an external LED/LCD, depending on the firmware 18 LED3 O configuration LED4/LCD4 display segment that drives an external LED/LCD, depending on the firmware 19 LED4 O configuration LED5/LCD5 display segment that drives an external LED/LCD, depending on the firmware 20 LED5 O configuration 21 GPIO A I/O Configurable Input or Output. If not used, tie to VSS. 22 VSS — Negative supply voltage 23 VSS — Negative supply voltage Master reset input that forces the device into reset when held low. This pin must be held high for 24 MRST I normal operation. 25 VSS — Negative supply voltage 26 VCC P Positive supply voltage RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of 27 RBI P short circuit condition. 28 GPIO B I/O Configurable Input or Output. If not used, tie to VSS. 29 ADREN O Optional digital signal enables address detection measurement to reduce power consumption. 30 SMBA IA Optional SMBus address detection input. If this pin is not used, then it should be tied to VSS. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq78350-R1 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |