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DP8390D Arkusz danych(PDF) 54 Page - National Semiconductor (TI) |
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DP8390D Arkusz danych(HTML) 54 Page - National Semiconductor (TI) |
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54 / 56 page ![]() 150 Switching Characteristics (Continued) Serial TimingTransmit (Collision) TLF8582 – 92 Symbol Parameter Min Max Units tcolw Collision Detect Width 2 txcyc cycles tcdj Delay from Collision to First 8 txcyc Bit of Jam (Note 1) cycles tjam Jam Period (Note 2) 32 txcyc cycles Note 1 The NIC must synchronize to collision detect If the NIC is in the middle of serializing a byte of data the remainder of the byte will be serialized Thus the jam pattern will start anywhere from 1 to 8 TXC cycles after COL is asserted Note 2 The NIC always issues 32 bits of jam The jam is all 1’s data Reset Timing TLF8582 – 93 Symbol Parameter Min Max Units rstw Reset Pulse Width (Note 1) 8 BSCK Cycles or TXC Cycles (Note 2) Note 1 The RESET pulse requires that BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several registers are affected by RESET Consult the register descriptions for details Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low If BSCK k TXC then RESET e 8 c BSCK If TXC k BSCK then RESET e 8 c TXC 54 |
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