3.0 ÛH

10 ÛF

4.7 ÛF

LM3208

SNVS404B – APRIL 2006 – REVISED MARCH 2013

www.ti.com

Figure 37. Evaluation Board Layout

Board Layout Flow

highest priority.

2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second

priority.

3. The above layout patterns should be placed on the component side of the PCB to minimize parasitic

inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between

C1(+) and C1(–) land patterns. If vias are used in these large current paths, multiple via-holes should be

used if possible.

4. Connect C1(–), C2(–) and PGND with wide GND pattern. This pattern should be short, so C1(–), C2(–), and

PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes

as possible.

5. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If

possible, connect SGND to the common port of C1(–), C2(–) and PGND.)

7. The FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a

shield.

NOTE

The evaluation board shown in Figure 37 for the LM3208 was designed with these

considerations, and it shows good performance. However some aspects have not been

optimized because of limitations due to evaluation-specific requirements. The board can

be used as a reference. Please refer questions to a TI representative.

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