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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TMS320C31PQL Arkusz danych(PDF) 23 Page - Texas Instruments |
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TMS320C31PQL Arkusz danych(HTML) 23 Page - Texas Instruments |
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23 / 48 page  TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS SPRS035B – MARCH 1996 – REVISED JANUARY 1999 23 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XF0 and XF1 timing when executing SIGI The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI. The numbers shown in Figure 17 correspond with those in the NO. column of the tables below. timing parameters for XF0 and XF1 when executing SIGI for TMS320C31 (see Figure 17) NO. ’LC31-33 ’C31-40 ’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 29 td(H3H-XF0L) Delay time, H3 high to XF0 low 15 13 12 11 8 ns 30 td(H3H-XF0H) Delay time, H3 high to XF0 high 15 13 12 11 8 ns 31 tsu(XF1-H1L) Setup time, XF1 before H1 low 10 9 9 8 6 ns 32 th(H1L-XF1) Hold time, XF1 after H1 low 0 0 0 0 0 ns H3 H1 Fetch SIGI Decode Read Execute XF0 XF1 31 32 29 30 Figure 17. Timing for XF0 and XF1 When Executing SIGI |
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