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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ST7FLCD1 Arkusz danych(PDF) 45 Page - STMicroelectronics |
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ST7FLCD1 Arkusz danych(HTML) 45 Page - STMicroelectronics |
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45 / 95 page  45/95 ST7FLCD1 PWM Generator Equations: This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. This provides an analog voltage proportional to the average charge through the external capacitor. Thus for a higher mark/space ratio (High time much greater than Low time) the average output voltage is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable. With: REXT = 1 kW fPWM = fCPU / (256 - ARR) fCPU = 8 MHz VDD = 5 V Worst case, PWM Duty Cycle 50% Table 16: Pulse WIdth in tCPU Pulse WIdth in tCPU DCR ³ ARR DCR - ARR + 1 DCR = ARR 1 DCR < ARR 0 (Output will not toggle) Table 17: 8-bit PWM Ripple after Filtering CEXT VRIPPLE 470 nF 60 mV 1µF 27mV 4.7 µF 6 mV Duty Cycle = DCR + 1 256 - ARR VRIPPLE = (1 - e 1/(2 x CEXT x REXT x fPWM))2 |1 - e 1/(CEXT x REXT x fPWM)| x VDD |
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