LP3936

SNVS259D – NOVEMBER 2003 – REVISED MAY 2013

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Logic Interface Characteristics (1.65V

≤ V

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL

Input Low Level

0.35

V

Input High Level

V

Logic Input Current

−1.0

1.0

µA

Clock Frequency

200

kHz

MicroWire Mode

4

MHz

LOGIC OUTPUTS DO, CS

Output Low Level

0.3

0.6

V

Output High Level

V

Output Leakage Current

1.0

µA

(1)

Control Interface

The LP3936 supports two different interfaces modes:

1)

MicroWire/SPI interface

2)

User can define the interface by MW_SEL pin. The pin configuration will also change depending on which

interface is selected. The following table shows the selections for both interface modes.

MW_SEL

Interface

Pin Configuration

Comment

1

MicroWire/SPI

SCL

(clock)

DI

(data in)

DO

(data out)

CS

(chip select)

0

SCL

(clock)

Use pull up resistor for SCL

CS = SDA

(data in/out)

Use pull up resistor for SDA

MicroWire/SPI Interface

The Microwire transmission consists of 16-bit Write and Read Cycles. One cycle consists of 7 Address bits, 1

Read/Write (R/W) bit and 8 Data bits. Read is done in two cycles: address is provided in the first cycle and the

data is sent out on the next cycle. R/W bit high state defines a Write Cycle and low defines a Read Cycle. DO

output is normally in high-impedance state and it is active only during Write and Read Cycles. A pull-up or pull-

down resistor may be needed in DO line if a floating logic signal can cause unintended current consumption in

other circuits where DO is connected.

The Address and Data are transmitted MSB first. The Chip Select signal CS must be low during the Cycle

transmission. CS resets the interface when high and it has to be taken high between successive Cycles. Data is

clocked in on the rising edge of the SCL clock signal, while data is clocked out on the falling edge of SCL.

The MicroWire interface mode can also support SPI interface. The difference with normal SPI interface is that in

LP3936 the Read operation from a new address needs two read cycles. If repetitive reads are made from the

same address, a correct value is obtained on every read cycle.

8

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