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CS5212D Arkusz danych(PDF) 12 Page - ON Semiconductor

Numer części CS5212D
Szczegółowy opis  Low Voltage Synchronous Buck Controller
PDF  16 Pages
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Producent  ONSEMI [ON Semiconductor]
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CS5212D Arkusz danych(HTML) 12 Page - ON Semiconductor

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CS5212
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12
Boost Component Selection for Upper and Lower
FET Gate Drive
The boost (BST) pin provides for application of a higher
voltage to drive the upper FET. This voltage may be
provided by a fixed higher voltage or it may be generated
with a boost capacitor and charging diodes, as shown in
Figure 1. The voltage in the boost configuration would be
the summation of the voltage from the charging diodes and
the output voltage swing. Care must be taken to keep the
peak voltage with respect to ground less than 20 V peak. The
capacitor value should be ten times larger than the
capacitance of the top FET. The boost circuit requires a
modification to achieve startup. See Rpull–up Selection for
boost circuit startup.
Rpull–up Value Selection for Boost Circuit Startup
The CS5212 application circuit incorporates a pull–up
resistor, R7, into the boost circuitry. This resistor is essential
to achieving startup of the boost circuit. At startup, the
GATE(H) output may be limited to 0.8 V, due to internal Vbe
drops. Until the boost circuitry charges up, the GATE(H)
output cannot provide sufficient Vgs to turn on the
MOSFET. A resistor from GATE(H) to BST allows
bypassing of the GATE(H) driver until the boost circuitry is
charged. The time constant, set by the pull–up resistor and
the Cin of the top MOSFET, must be fast enough to turn on
the MOSFET during the switching period. The following
equation is used to determine Rpull–up:
Rpull–up
t
1
(Cin
fSW)
where fSW is the switching frequency.
Choosing components according to this equation will
insure that approximately 63% of the boost voltage will be
applied to GATE(H) within one switching period. To start
charge pumping, the control MOSFET must pull up the
switching node above 0.6 V, two Schottky drops, which will
allow VC voltage to increase. Therefore, the voltage applied
by GATE(H) must be 0.6 V greater than Vth of the top FET.
Both high– and low–side switches must be sublogic level
MOSFETs with RDS(on) specified at 2.5 Vgs in order to
ensure proper up.



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