TNETX3150 datasheet(54/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

test registers

DIATST register at 0x00DD

BIT

Reserved

DPWRAP

INTWRAP

Reserved

Initial Values After Reset

BIT

NAME

FUNCTION

7–4

Reserved

DPWRAP

Duplex wrap mode. When DPWRAP = 1, all ports are forced into full-duplex mode and all ports can receive

frames they transmit. This enables external wrap testing at the PHY.

2–1

INTWRAP

Internal wrap mode. Ports 1–14 internally wrap back according to the following two-bit coding (INTWRAP

bit 2 and bit 1, respectively).

00 No internal wrapping

01 All ports internally wrapped except port 00 (uplink)

10 All ports internally wrapped except port 02

11 All ports internally wrapped except port 14

(The port that is not wrapped (00, 02, or 14) should be used to inject and observe test data frames from the

internally wrapped ports.)

Reserved

port N statistics at 0x80*N + 0x8000 through 0x80*N + 0x807F (N = port number in hex)

ADDRESS

Good RX frames

RX octets

0x80*N + 0x8000

+0x00–0x07

Multicast RX frames

Broadcast RX frames

0x80*N + 0x8000

+0x08–0x0F

RX align/code errors

RX CRC errors

0x80*N + 0x8000

+0x10–0x17

RX jabbers

Oversize RX frames

0x80*N + 0x8000

+0x18–0x1F

RX fragments

Undersize RX frames

0x80*N + 0x8000

+0x20–0x27

Frames 65–127

Frame 64

0x80*N + 0x8000

+0x28–0x2F

Frames 256–511

Frames 128–255

0x80*N + 0x8000

+0x30–0x37

Frames 1024–1518

Frames 512–1023

0x80*N + 0x8000

+0x38–0x3F

SQE test errors

Net octets

0x80*N + 0x8000

+0x40–0x47

Good TX frames

TX octets

0x80*N + 0x8000

+0x48–0x4F

Multi-collision TX frames

Single-collision TX frames

0x80*N + 0x8000

+0x50–0x57

Deferred TX frames

Carrier sense errors

0x80*N + 0x8000

+0x58–0x5F

Excessive collisions

Late collisions

0x80*N + 0x8000

+0x60–0x67

Multicast TX frames

Broadcast TX frames

0x80*N + 0x8000

+0x68–0x6F

TX data errors†

Filtered RX frames

0x80*N + 0x8000

+0x70–0x77

Address changes/mismatches

Address duplications

0x80*N + 0x8000

+0x78–0x7F

† The operation of this counter is controlled by the STMAP bit in the system control register.

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