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VT8231 Arkusz danych(PDF) 89 Page - List of Unclassifed Manufacturers

Numer części VT8231
Szczegółowy opis  SOUTH BRIDGE PC99 COMPLIANT
PDF  132 Pages
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Producent  ETC [List of Unclassifed Manufacturers]
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VT8231 Arkusz danych(HTML) 89 Page - List of Unclassifed Manufacturers

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VT8231
Preliminary Revision 0.8 October 29, 1999
-83-
Function 4 Regs - Power Management, SMBus and HWM
7HFKQRORJLHV ,QF
:H &RQQHFW
:H &RQQHFW
Function 4 Regs - Power Management, SMBus and HWM
This section describes the ACPI (Advanced Configuration and
Power Interface) Power Management system of the VT8231
which includes a System Management Bus (SMBus) interface
controller and Hardware Monitoring (HWM) subsystem. The
power management system of the VT8231 supports both ACPI
and legacy power management functions and is compatible
with the APM v1.2 and ACPI v1.0 specifications.
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
0-7
Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID.........................................................RO
0-7
Device ID
................ (3057h = ACPI Power Mgmt)
Offset 5-4 - Command.......................................................RW
15-8 Reserved
........................................ always reads 0
7
Address Stepping ........................................fixed at 0
6
Reserved (parity error response) ..................fixed at 0
5
Reserved (VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate ...................fixed at 0
3
Reserved (special cycle monitoring) ............fixed at 0
2Bus Master .................................................fixed at 0
1
Memory Space.............................................fixed at 0
0
I/O Space
.................................................fixed at 0
Offset 7-6 - Status ...........................................................RWC
15
Detected Parity Error ........................ always reads 0
14
Signalled System Error...................... always reads 0
13
Received Master Abort...................... always reads 0
12
Received Target Abort ...................... always reads 0
11
Signalled Target Abort ...................... always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .....................................default (fixed)
10 Slow
11 Reserved
8
Data Parity Detected.......................... always reads 0
7
Fast Back to Back Capable ............... always reads 1
6-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID (nnh) .............................................. RO
7-0
Silicon Revision Code
Offset 9 - Programming Interface (00h) .......................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 61h.
Offset A - Sub Class Code (00h) ....................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 62h.
Offset B - Base Class Code (00h) ...................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 63h.
Offset 0D - Latency Timer ............................................... RW
7-0
Timer Value .............................................. default = 0
Offset 0E - Header Type (00h).......................................... RO



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