FPD85310 datasheet(8/29 Pages) NSC

8 / 29 page

Functional Description (Continued)

face or custom gate interfaces can be implemented with the

nine GPOs. Note that GPO [8] must be used for output

blanking control.

Five registers provide the timing definition for each GPO.

The Horizontal Start register defines the output pixel number

for which the GPO output goes active. The Horizontal dura-

tion register determines how many clocks the output will re-

main active during the line. The Vertical Start register defines

at what line # the output becomes active, and the Vertical du-

ration register defines how many lines the output remains

active. Each output has a control register (bit 0) which de-

fines the GPO polarity (active high or low). Another bit in the

control register (bit 1) enables the “toggle” mode. This mode

is useful in REV generation when alternating polarity is re-

quired from line to line. Frame to Frame polarity changes are

made by programming an odd # in the vertical duration reg-

ister when in “toggle” mode.

Two of the General Purpose Outputs have additional capa-

bilities. GPO [8] controls output blanking and must be used

for this purpose. If output blanking is not desired, this register

must be programmed to always be active. White data gen-

eration (all “1” data) at the end of each frame is generated

when D6 register bit 7 is set. When this bit is set, white data

is output after line #768 if GPO [8] is active. GPO [0] is ca-

pable of performing line inversion on the output data. Bits

[5:3] of the Output Format Control register provides control

for this function.

See

APPENDIX A: GPO Programming Examples.

SERIAL EEPROM INTERFACE

The Serial EEPROM Interface controls the FPD85310 initial-

ization. If the EEPROM is not present (EESD and EESC are

pulled high), or if EEPROM address 80H is not “00”, the in-

ternal default values are used to initialize all programmable

functions of the FPD85310.

At power-up, the FPD85310 configures the internal program-

mable registers with data from the EEPROM. After the

FPD85310 is initialized, the EEPROM can be accessed by

the system in which display configuration and manufacturing

information can be obtained. The EEPROM can be pro-

grammed “in system” providing quick evaluation of different

display timing.

External access to the EEPROM must be preceded by ap-

plying a “1” to pin TEST [2] in order to interrupt the

FPD85310 download.

The FPD85310 initialization data begins at EEPROM ad-

dress 80H. The first 128 bytes (0-7F) are reserved for dis-

play identification data.

A power-up delay can be programmed using bits [6:5] of the

Input Format Control Register. This delays outputting (driv-

ing) of the data and control for up to 5 frame times after re-

set. The TEST [2] pin must be low for a power-up delay to

occur.

VERTICAL/HORIZONTAL REFERENCE GENERATOR

AND FAILURE DETECTION

This block provides Vertical and Horizontal Reference points

for the Timing Control Function. VSYNC, HSYNC and ENAB

along with programmable control from the input control reg-

ister bits 0 and 1 (FIX HORIZONTAL and FIX VERTICAL)

are used to determine when the video from the host is valid.

Three input modes are supported. See

Table 1.

Fixed Vertical, Fixed Horizontal

The horizontal timing is fixed and determined by the Horizon-

tal Backporch register. The vertical timing is also fixed and

determined by the Vertical Backporch register. ENAB is ig-

nored and is not necessary.

Fixed Vertical, ENAB Controlled Horizontal

The horizontal timing is controlled by the ENAB timing. The

vertical timing is fixed and determined by the Vertical Back-

porch register.

ENAB Only

In ENAB Only timing, VSYNC and HSYNC are ignored. All

timing is derived from the ENAB signal.

Failure Detection

The FPD85310 detects the loss of (necessary) control from

the system. VSYNC, HSYNC, ENAB, and CLK are moni-

tored for failure conditions. Failure condition is detected

whenever the input clock stops or when control necessary

for the operational mode is inactive. Failure conditions result

in outputting a default video stream to the panel. Depending

on the mode, loss of CLK, ENAB, HSYNC and/or VSYNC

will result in fail condition output timing. The FPD85310 has

an internal oscillator used for input clock failure detection. If

the input clock quits toggling, the internal oscillator gener-

ates the control timing to the column drivers and row drivers.

The internal ring oscillator is disabled when a “1” is applied to

the TEST [3] pin. This will, of course, disable the clock failure

detection capability of the FPD85310. Further description of

the failure detection modes is given in

Table 4.

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