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Revision 3.1

Integrated Functions (Continued)

4.5.1

Display FIFO

The display controller contains a large (64x64 bit) FIFO for

queuing up display data from the memory controller as it

is required for output to the screen. The memory control-

ler must arbitrate between the display controller requests

and other requests for memory access from the micropro-

cessor core, L1 cache controller, and the graphics pipe-

line.

Since display data is required in real time, this data is the

highest priority in the system. Without efficient memory

management, system performance would suffer dramati-

cally due to the constant display-refresh requests from the

display controller. The large size of the display FIFO is

desirable so that the FIFO may primarily be loaded during

times when there is no other request pending to the

DRAM controller and so that the memory controller can

stay in page mode for a long period of time when servicing

the display FIFO. When a priority request from the cache

or graphics pipeline occurs, if the display FIFO has

enough data queued up, the DRAM controller can imme-

diately service the request without concern that the dis-

play FIFO will underflow. If the display FIFO is below a

programmable threshold, a high-priority request will be

sent to the DRAM controller, which will take precedence

over any other requests that are pending.

The display FIFO is 64 bits wide to accommodate high-

speed burst read operations from the DRAM controller at

maximum memory bandwidth. In addition to the normal

pixel data stream, the display FIFO also queues up cursor

patterns.

4.5.2

Compression Technology

To reduce the system memory contention caused by the

display refresh, the display controller contains compres-

sion and decompression logic for compressing the frame

buffer image in real time as it is sent to the display. It com-

bines this compressed display buffer into the extra off-

screen memory within the graphics memory aperture.

Coherency of the compressed display buffer is maintained

by use of dirty and valid bits for each line. The dirty and

valid RAM is contained on-chip for maximum efficiency.

Whenever a line has been validly compressed, it will be

retrieved from the compressed display buffer for all future

accesses until the line becomes dirty again. Dirty lines will

be retrieved from the normal uncompressed frame buffer.

The compression logic has the ability to insert a program-

mable number of "static" frames, during which time dirty

bits are ignored and the valid bits are read to determine

whether a line should be retrieved from the frame buffer or

compressed display buffer. The less frequently the dirty

bits are sampled, the more frequently lines will be

retrieved from the compressed display buffer. This allows

a programmable screen image update rate (as opposed to

refresh rate). Generally, an update rate of 30 frames per

second is adequate for displaying most types of data,

including real- time video. However, if a flat panel display

is used that has a slow response time, such as 100 ms,

the image need not be updated faster than ten frames per

second, since the panel could not display changes

beyond that rate.

The compression algorithm used in the GXm processor

commonly achieves compression ratios between 10:1 and

20:1, depending on the nature of the display data. This

high level of compression provides higher system perfor-

mance by reducing typical latency for normal system

memory access, higher graphics performance by increas-

ing available drawing bandwidth to the DRAM array, and

much lower power consumption by significantly reducing

the number of off-chip DRAM accesses required for

refreshing the display. These advantages become even

more pronounced as display resolution, color depth, and

refresh rate are increased and as the size of the installed

DRAM increases.

As uncompressed lines are fed to the display, they will be

compressed and stored in an on-chip compressed line

buffer (64x32 bits). Lines will not be written back to the

compressed display buffer in the DRAM unless a valid

compression has resulted, so there is no penalty for

pathological frame buffer images where the compression

algorithm breaks down.

4.5.3

Motion Video Acceleration Support

The display controller of the GXm processor supports the

CS5530 and future I/O companion chips’ hardware motion

video acceleration by reading the off-screen video buffer

and serializing the video data onto the RAMDAC port. The

display controller supplies video data to the I/O compan-

ion chips in either interleaved YUV4:2:2 format or

RGB5:6:5 format. The I/O companion chips can then

scale and filter the data, apply color space conversion to

YUV data, and mix the video data with graphics data also

supplied by the display controller.

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