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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PIFE32251B-R68MS Arkusz danych(PDF) 4 Page - Texas Instruments |
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PIFE32251B-R68MS Arkusz danych(HTML) 4 Page - Texas Instruments |
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4 / 157 page  4 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Revision History Copyright © 2014–2016, Texas Instruments Incorporated • Added VR2 DVS specifications ................................................................................................... 27 • Added VR2_Powergood Mask specifications ................................................................................... 28 • Added VR2_Force PWM specifications ......................................................................................... 29 • Deleted High-side output peak current limit ..................................................................................... 29 • Added Current limit (Vsw - PGND) voltage specifications ..................................................................... 29 • Added Negative current limit (Vsw - PGND) voltage specifications .......................................................... 30 • Deleted VR3 Controller Power Low-side output valley current limit .......................................................... 30 • Deleted VR3 Controller Power Soft-Start total turn-on time ................................................................... 30 • Added VR3 Soft-Start specifications ............................................................................................. 30 • Changed VR3 Controller Power Soft-Start delay time values ................................................................ 30 • Added VR3 DVS specifications ................................................................................................... 30 • Added VR3 Decay exit specifications ............................................................................................ 31 • Added VR3_Powergood deglitch ................................................................................................. 32 • Added VR3_Powergood Mask specifications ................................................................................... 32 • Added VR3_Force PWM specifications ......................................................................................... 32 • Deleted VR3 Controller Control VR3 delay time from enable to switching .................................................. 33 • Deleted Low-side output valley current limit ..................................................................................... 34 • Added Current limit (Vsw - PGND) voltage specifications ..................................................................... 34 • Added Negative current limit (Vsw - PGND) voltage specifications .......................................................... 34 • Deleted VR4 Controller Power Soft-Start total turn-on time ................................................................... 35 • Added VR4 Soft-Start specifications ............................................................................................. 35 • Changed VR4 Controller Power Soft-Start delay time values ................................................................ 35 • Added VR4 DVS specifications ................................................................................................... 35 • Added VR4_Powergood deglitch ................................................................................................. 36 • Added VR4_Powergood Mask specifications ................................................................................... 36 • Added VR4_Force PWM specifications ......................................................................................... 37 • Added LDO1_Powergood deglitch ............................................................................................... 38 • Deleted High-side output peak current limit ..................................................................................... 39 • Added Current limit (Vsw - PGND) voltage specifications ..................................................................... 39 • Added Negative current limit (Vsw - PGND) voltage specifications .......................................................... 39 • Deleted VR5 Controller Power Low-side output valley current limit .......................................................... 39 • Added VR5 Soft-Start specifications ............................................................................................. 40 • Added VR5 DVS specifications ................................................................................................... 40 • Added VR5_Powergood deglitch ................................................................................................. 41 • Added VR5_Powergood Mask specifications ................................................................................... 41 • Added VR5_Force PWM specifications ......................................................................................... 42 • Added 16 ms delay from ENVR3 to start switching of VR3 in Figure 5-1 ................................................... 45 • Changed Table 6-1 ................................................................................................................. 52 • Added Section 6.3.2 ................................................................................................................ 53 • Added Section 6.3.3 ................................................................................................................ 54 • Added Section 6.3.4 ................................................................................................................ 55 • Added Section 6.3.5 ................................................................................................................ 56 • Added Section 6.3.6 ................................................................................................................ 57 • Added Section 6.3.7 ................................................................................................................ 57 • Added Section 6.3.8 ................................................................................................................ 58 • Added Section 6.3.9 ................................................................................................................ 60 • Added Section 6.3.10 .............................................................................................................. 61 • Added Section 6.3.11 .............................................................................................................. 63 • Added Section 6.3.12 .............................................................................................................. 64 • Added Figure 6-15 and following paragraph ..................................................................................... 66 • Deleted last paragraph and equation from Section 6.3.13.4 ................................................................. 68 • Changed and moved Section 6.4 ................................................................................................. 70 • Moved Section 6.5.1 to Section 6.5 ............................................................................................... 72 • Added Table 6-3 .................................................................................................................... 75 • Changed register formatting, reordered registers, and deleted Default from field descriptions .......................... 77 • Changed ? 1V to >1.05V in bit 6:3 description in Table 6-47 ................................................................ 110 • Changed ? 1V to >1.05V in bit 6:3 description in Table 6-48 ................................................................ 111 • Changed ? 1V to >1.05V in bit 6:3 description in Table 6-49 ................................................................ 112 • Changed ? 1V to >1.05V in bit 6:3 description in Table 6-50 ................................................................ 113 • Changed ? 1V to >1.05V in bit 6:3 description in Table 6-51 ................................................................ 114 |
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