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DP7221 Arkusz danych(PDF) 3 Page - Copal Electronics

Numer części DP7221
Szczegółowy opis  Dual Digital Potentiometer
PDF  16 Pages
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Producent  COPAL [Copal Electronics]
Strona internetowa  http://www.nidec-copal-electronics.com/e
Logo COPAL - Copal Electronics

DP7221 Arkusz danych(HTML) 3 Page - Copal Electronics

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DP7221
© NIDEC COPAL ELECTRONICS CORP.
3
Doc. No. MD-2113 Rev. K
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS
(1)
s
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R
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P
C
°
5
2
1
+
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5
5
-
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0
5
1
+
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5
6
-
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p
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e
T
e
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a
r
o
t
S
Voltage on any Pin with Respect to VSS
(2)
-2.0 to +VCC +2.0
V
VCC
V
0
.
7
+
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0
.
2
-
d
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r
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o
t
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p
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R
h
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Package Power Dissipation Capability (TA = 25°C)
1.0
W
C
°
0
0
3
)
s
0
1
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1
±
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RECOMMENDED OPERATING CONDITIONS
Vcc = +2.5V to +6V
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Operating Ambient Temperature (Industrial)
-40 to +85
°C
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
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RPOT
Potentiometer Resistance (-00)
100
k
RPOT
Potentiometer Resistance (-50)
50
k
RPOT
Potentiometer Resistance (-10)
10
k
RPOT
Potentiometer Resistance (-2.5)
2.5
k
Potentiometer Resistance Tolerance
±20
%
RPOT
%
1
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IW
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6
±
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W
RW
Wiper Resistance
IW = +3mA @ VCC =3V
300
RW
Wiper Resistance
IW = +3mA @ VCC = 5V
80
150
VTERM
Voltage on any RH or RL Pin
VSS =0V
GND
VCC
VN
/
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4
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N
Hz
%
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Absolute Linearity
(5)
RW(n)(actual) -R(n)(expected)
(8)
±1
LSB
(7)
Relative Linearity
(6)
RW(n+1) -[RW(n)+LSB]
(8)
±0.2
LSB
(7)
TCRPOT
Temperature Coefficient of RPOT
(4)
±300
ppm/°C
TCRATIO
Ratiometric Temp. Coefficient
(4)
20
ppm/°C
CH/CL/CW Potentiometer Capacitances
(4)
10/10/25
pF
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F
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f
POT =50k
0.4
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(8) n = 0, 1, 2, ..., 63



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