LM40 datasheet(25/27 Pages) NSC

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3.0 Application Hints (Continued)

3.1 DIODE NON-IDEALITY

3.1.1 Diode Non-Ideality Factor Effect on Accuracy

When a transistor is connected as a diode, the following

relationship holds for variables V

BE, T and If:

where:

•

q = 1.6x10

−19 Coulombs (the electron charge),

•

T = Absolute Temperature in Kelvin

•

k = 1.38x10

−23joules/K (Boltzmann’s constant),

•

η is the non-ideality factor of the process the diode is

manufactured on,

•

S = Saturation Current and is process dependent,

•

f= Forward Current through the base emitter junction

•

BE = Base Emitter Voltage drop

In the active region, the -1 term is negligible and may be

eliminated, yielding the following equation

In the above equation,

η and I

S are dependant upon the

process that was used in the fabrication of the particular

diode. By forcing two currents with a very controlled ration

(N) and measuring the resulting voltage difference, it is

possible to eliminate the I

S term. Solving for the forward

voltage difference yields the relationship:

The non-ideality factor,

η, is the only other parameter not

accounted for and depends on the diode that is used for

measurement. Since

∆V

BE is proportional to both

η and T,

the variations in

η cannot be distinguished from variations in

temperature. Since the non-ideality factor is not controlled by

the temperature sensor, it will directly add to the inaccuracy

of the sensor. For the Pentium III Intel specifies a ±1%

variation in

η from part to part. As an example, assume a

temperature sensor has an accuracy specification of ±3˚C at

room temperature of 25 ˚C and the process used to manu-

facture the diode has a non-ideality variation of ±1%. The

resulting accuracy of the temperature sensor at room tem-

perature will be:

ACC = ± 3˚C+(±1% of 298 ˚K) = ±6˚C

The additional inaccuracy in the temperature measurement

caused by

η, can be eliminated if each temperature sensor is

calibrated with the remote diode that it will be paired with.

The following table shows the variations in non-ideality for a

variety of processors.

Processor Family

η, non-ideality

Series

min

typ

max

Pentium II

1.0065 1.0173

Pentium III CPUID 67h

1.0065 1.0125

Pentium III CPUID

68h/PGA370Socket/Celeron

1.0057

1.008

1.0125

Pentium 4, 423 pin

0.9933 1.0045 1.0368

Pentium 4, 478 pin

0.9933 1.0045 1.0368

Pentium 4 on 0.13

micron process,

2-3.06GHz

1.0011 1.0021 1.0030 3.64

Ω

Pentium 4 on 90 nm

process

1.011

3.33

Ω

Pentium M Processor

(Centrino)

1.00151 1.00220 1.00289 3.06

Ω

MMBT3904

1.003

AMD Athlon MP model

1.002

1.008

1.016

3.2 PCB LAYOUT for MINIMIZING NOISE

In a noisy environment, such as a processor mother board,

layout considerations are very critical. Noise induced on

traces running between the remote temperature diode sen-

sor and the LM40 can cause temperature conversion errors.

Keep in mind that the signal level the LM40 is trying to

measure is in microvolts. The following guidelines should be

followed:

Place the 100 pF and 0.1 µF power supply bypass

capacitors as close as possible to the LM40’s power pin.

Place the recommended thermal diode 100 pF capacitor

as close as possible to the LM40’s D+ and D− pins.

Make sure the traces to the thermal diode 100 pF ca-

pacitor are matched.

The recommended 100 pF diode capacitor actually has

a range of 0 pF to 3.3 nF (see curve in Typical Perfor-

mance Characteristics for effect on accuracy). The av-

erage temperature accuracy will not degrade. Increasing

the capacitance will lower the corner frequency where

differential noise error affects the temperature reading

thus producing a reading that is more stable. Con-

versely, lowering the capacitance will increase the cor-

ner frequency where differential noise error affects the

temperature reading thus producing a reading that is

less stable.

20068417

FIGURE 8. Ideal Diode Trace Layout

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