IS25LP080D datasheet(71/108 Pages) ISSI

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IS25LP080D

IS25WP080D/040D/020D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/02/2016

8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET

The Software Reset operation is used as a system reset that puts the device in normal operating mode. During the

Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile

requires the Reset-Enable command followed by the Reset command. Any command other than the Reset

command after the Reset-Enable command will disable the Reset-Enable.

Execute the CE# pin low  sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives

CE# low again, sends the Reset command (99h), and pulls CE# high.

Only if the RESET# pin is enabled, Hardware Reset function is available.

For all other packages except the package with dedicated RESET# pin (or ball) option, the RESET# pin (or ball)

will be solely applicable in SPI mode and when the QE bit is disabled.

For the package with dedicated RESET# pin (or ball), the RESET# pin (or ball) is always applicable regardless of

the QE bit value in Status Register and HOLD#/RESET# selection bit (P7) in Read Register. The dedicated

RESET# pin has an internal pull-up resistor and may be left floating if not used. The RESET# pin (or ball) has the

highest priority among all the input signals and will reset the device to its initial power-on state regardless of the

state of all other pins (CE#, IOs, SCK, and WP#).

In order to activate Hardware Reset, the RESET# pin (or ball) must be driven low for a minimum period of tRESET

(1µs). Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external operations,

release the device from deep power down mode1, disable all input signals, force the output pin enter a state of high

impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter than 1µs, it may

still reset the device, however the 1µs minimum period is recommended to ensure the reliable operation. The

required wait time after activating a HW Reset before the device will accept another instruction (tHWRST) is the same

as the maximum value of tSUS (100µs).

The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can result

in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing

may vary. Recovery from a Write operation will require more latency than recovery from other operations.

Note1: The Status and Function Registers remain unaffected.

Figure 8.58 Software Reset Enable and Software Reset Sequence In SPI Mode (RSTEN, 66h + RST, 99h)

Instruction = 66h

CE#

SCK

Mode 3

Mode 0

Instruction = 99h

High Impedance

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