TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

22

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Valid Out

RAS

CAS

Address

W

OE

DQ1 – DQ4

Row

Column

Don’t Care

Valid

In

Column

tRASP

Valid

In

tRP

tCSH

tPRWC

tRCD

tCP

tCRP

tRSH

tASC

tCAH

tRAD

tASR

tCWD

tRAH

tAWD

tCWL

tRWL

tWP

tRWD

tCPA

tOEH

tDH

tDS

tAA

tRCS

tRAC

tCAC

tCLZ

tOEA

tOEZ

tOEH

tOED

tCAS

Valid Out†

tCPW

tRHCP

tOHO

† Output can go from high-impedance state to an invalid-data state prior to the specified access time.

NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.

Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing