FEDR45V064B-01

MR45V064B

2/20

PIN CONFIGURATION

Note:

Signal names that end with # indicate that the signals are negative-true logic.

PIN DESCRIPTIONS

Pin Name

Description

CS#

Chip Select (input, negative logic)

Latches an address by low input, activates the FeRAM, and enables a read or write

operation.

WP#

Write Protect( input , negative logic )

Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should

be fixed low or high in write-operations.

HOLD#

HOLD( input , negative logic )

Hold pin is used when the serial-communication suspended without disable the chip

select.

When

HOLD#

is

low

,the

serial-output

is

in

High-Z

status

and

serial-input/serial-clock are “Don

’t Care” . CS# should be low in hold operation.

SCK

Serial Clock

Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on

the rising edge and output occur on the falling edge.

SI

Serial input

SI pins are serial input pins for Operation-code , addresses ,and data-inputs .

SO

Serial output

SO pins are serial output pins.

Power supply

8-pin plastic SOP

CS#

SO

WP#

VSS

VCC

HOLD#

SCK

SI

1

8

2

7

3

6

4

5